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公开(公告)号：US20250070550A1
公开(公告)日：2025-02-27
申请号：US18803607
申请日：2024-08-13
Applicant: LAPIS Technology Co., Ltd.
Inventor： Satoru KUROTSU
Abstract: An RC circuit 110 is connected in series between VDD and GND. A RC circuit 120 is set with a time constant different from that of the RC circuit 110 connected in series between VDD and GND. In the inverter circuit 210, a potential is input between a resistance element 111 and a capacitance element 112. In the inverter circuit 220, a potential is input between a resistance element 121 and a capacitance element 122. In an NMOS transistor 310, an output of the inverter circuit 210 is input to a gate terminal, and a drain terminal is connected to VDD. In an NMOS transistor 320, an output of the inverter circuit 220 is input to a gate terminal, a drain terminal is connected with a source terminal of the NMOS transistor 310, and a source terminal is connected with GND.
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公开(公告)号：US20250037639A1
公开(公告)日：2025-01-30
申请号：US18784886
申请日：2024-07-25
Applicant: LAPIS Technology Co., Ltd.
Inventor： Kouya SUGIHARA
Abstract: A circuit includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.
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公开(公告)号：US20250008064A1
公开(公告)日：2025-01-02
申请号：US18753535
申请日：2024-06-25
Applicant: LAPIS Technology Co., Ltd.
Inventor： Tomoyuki ICHIKAWA
Abstract: A correction device including: a memory; and a processor coupled to the memory, the processor configured to: receive a modulated video signal; separate the modulated video signal into a color difference signal and a luminance signal; and in cases in which a luminance component change value in a given frequency band in a demodulated luminance signal, demodulated from the luminance signal, is a given threshold or greater, perform correction such that color difference components present in a demodulated color difference signal demodulated from the color difference signal and corresponding to the luminance components are emphasized, compared to cases in which the change value is less than the given threshold.
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公开(公告)号：US20240421364A1
公开(公告)日：2024-12-19
申请号：US18820467
申请日：2024-08-30
Applicant: LAPIS Technology Co., Ltd.
Inventor： Masato YAMAZAKI
IPC: H01M10/42
Abstract: In a battery monitoring system, when a communication interface circuit receives an output command for monitoring data of each cell according to an instruction from a battery management circuit, the output commands are simultaneously transmitted from a third connection port and a fourth connection port of the communication interface circuit to both of a first connection port of a group and a second connection port of the group in a battery pack unit group, communication control is performed such that the output commands are transmitted to all of plural battery pack units, and communication data output from each of the plural battery pack units is output from both of the connection ports.
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公开(公告)号：US20240378169A1
公开(公告)日：2024-11-14
申请号：US18660191
申请日：2024-05-09
Applicant: LAPIS Technology Co., Ltd
Inventor： Kunihiro HARAYAMA
IPC: G06F13/42
Abstract: A master device transmits a clock signal to a first slave device together with a write data signal including write data pieces respectively corresponding to slave devices connected in cascade. Each slave device includes a buffer that receives the clock signal, outputs an amplified clock signal, and transmits the clock signal to a next stage slave device, and an information acquisition circuit that acquires information data pieces and reads them as read data pieces. The slave devices take in a series of write data pieces included in the write data signal while shifting them at the timing of the clock signal output from each of the master device and the buffer and transmit a read data signal including a series of read data pieces read from each information acquisition circuit to the master device via the first slave device while shifting them at the timing of the clock signal group.
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Patent Agency Ranking
公开(公告)号：US20240364122A1
公开(公告)日：2024-10-31
申请号：US18642827
申请日：2024-04-23
Applicant: LAPIS Technology Co., Ltd.
Inventor： Ryo MATSUMOTO
IPC: H02J7/00
CPC classification number: H02J7/0016 , H02J7/007182
Abstract: A cell balance switch circuit 17 includes: electrodes 23; conductive wires 25, respectively connected with the electrodes 23; and cell balance switches 27, connected between adjacent two conductive wires among the conductive wires 25. Each cell balance switch 27 includes: a first transistor 31, connected between adjacent conductive wires 25; a bias wire 33, connected with a gate (G) of the first transistor 31; and a suppression circuit 35, connected between the bias wire 33 and the conductive wire 25. The suppression circuit 35 includes a switch 37 temporarily connecting the bias wire 33 and the conductive wire 25 responsive to a voltage change of the conductive wire 25.
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公开(公告)号：US20240331656A1
公开(公告)日：2024-10-03
申请号：US18609715
申请日：2024-03-19
Applicant: LAPIS Technology Co., Ltd.
Inventor： Kenji Yanagawa
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G2310/08 , G09G2320/0673 , G09G2330/12
Abstract: A source driver of the disclosure supplies a display device having a plurality of display cells with gradation voltages corresponding to respective luminance levels for the display cells indicated by a video signal. The source driver includes a gamma voltage generating circuit and a gradation voltage determination circuit. The gamma voltage generating circuit includes a resistor voltage dividing circuit with a plurality of output terminals. The plurality of output terminals output respective reference voltages divided according to gamma curve characteristics for generating the gradation voltages. The gradation voltage determination circuit measures an electric potential difference between one pair among the plurality of output terminals and determines whether or not the electric potential difference corresponds to a reference voltage group based on the gamma curve characteristics.
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公开(公告)号：US20240329868A1
公开(公告)日：2024-10-03
申请号：US18619596
申请日：2024-03-28
Applicant: LAPIS Technology Co., Ltd.
Inventor： Yusuke HATA
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: For a memory space including data words for storing data associated with a block number for identifying plural blocks and a data address for each of the blocks, in a memory configuration provided with a memory group configured including plural data words each respectively stored with data associated with the data address belonging to each of the respective block groups, and including at least one spare data word, in cases in which data of the data address is designated to be updated, a computer writes data after updating of the designated data address to a data word 1C in a memory group containing the data word for storing the data of the designated data address.
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公开(公告)号：US20240329107A1
公开(公告)日：2024-10-03
申请号：US18615544
申请日：2024-03-25
Applicant: LAPIS Technology Co., Ltd.
Inventor： Koki NAKANISHI
IPC: G01R27/26 , H03K17/955
CPC classification number: G01R27/2605 , H03K17/955
Abstract: A capacitance measurement device including: a charging switch that connects a measurement node, connected to one-end of a measurement target capacitor, with a power source node that applies a first voltage in an ON state, and disconnects the measurement node from the power source node in an OFF state; a constant current circuit that causes a current of a constant magnitude to flow from the measurement node; a comparator that compares a voltage of the measurement node with a second voltage lower than the first voltage; and a processing unit that performs processing to measure a lapse time from when the charging switch has changed to the OFF state until an output of the comparator flips.
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公开(公告)号：US20240321169A1
公开(公告)日：2024-09-26
申请号：US18604531
申请日：2024-03-14
Applicant: LAPIS Technology Co., Ltd.
Inventor： Hiroshi TSUCHI
IPC: G09G3/20 , H03K19/003
CPC classification number: G09G3/2092 , H03K19/00361 , G09G2300/0426 , G09G2310/0291 , G09G2310/08 , G09G2330/021 , G09G2330/06
Abstract: The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.
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