公开(公告)号：US06385079B1

公开(公告)日：2002-05-07

申请号：US09944680

申请日：2001-08-31

Applicant: Lung T. Tran

Inventor： Lung T. Tran

IPC: G11C1100

CPC classification number: G11C11/15

Abstract: A method for designing a resistive random access memory array in which elements are selected with values of resistances that are correlated to maintain a signal-to-noise ratio of 20 decibels or more for the array. A plurality of memory cells are selected and spaced from each other in a matrix of rows and columns, each memory cell being selected to have a junction resistance value of between 0.25 megaohms and 3.60 megaohms. A plurality of conductive row lines are selected and connected between a number N of memory cells in each row, each row and column line being selected to have a row or column unit line resistance value below 0.38 ohms, so that the values of junction resistance are correlated with the values of the row and column unit line resistance to provide a signal-to-noise ratio of 20 decibels or more for the memory array. The values of the row and column unit line resistance are selected so that the total row line resistance for each row is approximately equal to the total column line resistance for each column. The ratio of the junction resistance to the unit line resistance is approximately five million to one, in order to maintain a signal-to-noise ratio of at least 20 decibels in the resistive memory array. For an equal number N of row and column elements, the total row or column line resistance must be greater than approximately five million to N. If N is equal to approximately 1000, the ratio of junction resistance to total row or column line resistance must be approximately 5,000 or greater.

Abstract translation: 一种用于设计电阻随机存取存储器阵列的方法，其中元件被选择为具有相关联的电阻值，以保持阵列的20分贝或更高的信噪比。 选择多个存储单元并以行和列的矩阵彼此间隔开，每个存储单元被选择为具有0.25兆欧和3.60兆欧姆之间的结电阻值。 选择多个导电行线并连接在每行中的N个存储单元之间，每行和列线被选择为具有低于0.38欧姆的行或列单位线电阻值，使得结电阻值为 与行和列单位线电阻的值相关，以提供存储器阵列的20分贝或更多的信噪比。 选择行和列单位线电阻的值，使得每行的总行线电阻大致等于每列的总列线电阻。 为了在电阻式存储器阵列中保持至少20分贝的信噪比，结电阻与单位线电阻的比值约为500万比1。 对于相等数量的行和列元素，总行或列线电阻必须大于约500万到N。如果N等于大约1000，则结电阻与总行或列线电阻的比率必须为 约5,000或更大。

公开(公告)号：US06356477B1

公开(公告)日：2002-03-12

申请号：US09771857

申请日：2001-01-29

Applicant: Lung T. Tran

Inventor： Lung T. Tran

IPC: G11C1100

CPC classification number: H01L27/224 ,  G11C11/15 ,  G11C2213/72 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/228

Abstract: An information storage device includes a resistive cross point array of memory elements and a plurality of devices (e.g., diodes, transistors) for blocking sneak path currents in the array during read operations. Each blocking device is connected to and shared by a group of memory elements in the array.

Abstract translation: 信息存储设备包括存储器元件的电阻交叉点阵列和用于在读取操作期间阻挡阵列中的潜行路径电流的多个器件（例如，二极管，晶体管）。 每个阻塞设备连接到阵列中的一组存储器元件并由该组存储器元件共享。

公开(公告)号：US06169686A

公开(公告)日：2001-01-02

申请号：US08974925

申请日：1997-11-20

Applicant: James A. Brug ,  Lung T. Tran ,  Thomas C. Anthony ,  Manoj K. Bhattacharyya ,  Janice Nickel

Inventor： James A. Brug ,  Lung T. Tran ,  Thomas C. Anthony ,  Manoj K. Bhattacharyya ,  Janice Nickel

IPC: G11C1114

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  H01L27/224

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

公开(公告)号：US5309304A

公开(公告)日：1994-05-03

申请号：US894394

申请日：1992-06-05

Applicant: Steven L. Naberhuis ,  Ralph Simmons ,  Robert J. Davidson ,  Victor W. Hesterman ,  Lung T. Tran ,  Giora J. Tarnopolsky

Inventor： Steven L. Naberhuis ,  Ralph Simmons ,  Robert J. Davidson ,  Victor W. Hesterman ,  Lung T. Tran ,  Giora J. Tarnopolsky

IPC: G01D5/245 ,  G01R33/09 ,  G11B5/39 ,  H01F10/08 ,  H01L43/08 ,  G11B5/127

CPC classification number: G11B5/3954 ,  G11B5/399

Abstract: In a magnetoresistive transducer, a conductor configuration in which magnetic fields in the conductors are oriented in the same direction to provide symmetric track profiles and improved track edge response. Conductor area at the transducer air bearing surface is also minimized to eliminate shorting and improve device yield and reliability. In one embodiment of the invention, inductive pickup is minimized by limiting the active width of magnetoresistive sensing elements through conductor placement. Another embodiment of the invention, useful for applications involving dual stripe magnetoresistive transducers, minimizes inductive pickup by providing relatively large conductors for each magnetoresistive stripe, arranged in parallel with each other and coupled differentially to cancel inductive pickup through common mode rejection.

Abstract translation: 在磁阻换能器中，导体配置中导体中的磁场被定向在相同的方向上以提供对称的轨道轮廓和改进的轨道边缘响应。 传感器空气轴承表面的导体面积也被最小化，以消除短路并提高器件的产量和可靠性。 在本发明的一个实施例中，通过通过导线放置来限制磁阻感测元件的有源宽度来使电感拾取器最小化。 可用于涉及双条磁阻传感器的应用的本发明的另一个实施例通过为每个磁阻条提供相对较大的导体使彼此并联布置并且通过共模抑制来抵消电感拾取器而被耦合地极化电感拾取。