Thermal management package and method

    公开(公告)号:US11257734B2

    公开(公告)日:2022-02-22

    申请号:US16816874

    申请日:2020-03-12

    Inventor: Damian McCann

    Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.

    SYSTEM AND METHOD FOR AUTO-RECOVERY IN LOCKSTEP PROCESSORS

    公开(公告)号:US20210373898A1

    公开(公告)日:2021-12-02

    申请号:US17075493

    申请日:2020-10-20

    Inventor: Pierre Selwan

    Abstract: A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.

    Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification

    公开(公告)号:US20210173993A1

    公开(公告)日:2021-06-10

    申请号:US17111218

    申请日:2020-12-03

    Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

    Analog switch for transmitting high voltage signals without utilizing high voltage power supplies

    公开(公告)号:US10756719B2

    公开(公告)日:2020-08-25

    申请号:US14919000

    申请日:2015-10-21

    Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of −100V to +100V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.

    Output current control in a boundary conduction mode buck converter
    68.
    发明授权
    Output current control in a boundary conduction mode buck converter 有权
    输出电流控制在边界导通模式降压转换器

    公开(公告)号:US09337725B2

    公开(公告)日:2016-05-10

    申请号:US13947894

    申请日:2013-07-22

    CPC classification number: H02M3/156 H02M3/155 H05B33/0818

    Abstract: A switching power converter has an input voltage source. An output load is coupled to the input voltage source. An inductive element is coupled to the load. A switch is coupled to the inductive element. A control circuit is coupled to the switch and the inductive element for activating and deactivating the switch, the control circuit activating and deactivating the switch based on a negative voltage drop across a resistive element of the control circuit.

    Abstract translation: 开关电源转换器具有输入电压源。 输出负载耦合到输入电压源。 电感元件耦合到负载。 开关耦合到电感元件。 控制电路耦合到开关和感应元件,用于启动和停用开关,控制电路基于控制电路的电阻元件上的负电压降激活和去激活开关。

    Audio spectrum analyzer implemented with a minimum number of multiply operations
    70.
    发明申请
    Audio spectrum analyzer implemented with a minimum number of multiply operations 有权
    音频频谱分析仪采用最小数量的乘法运算

    公开(公告)号:US20030179820A1

    公开(公告)日:2003-09-25

    申请号:US09972558

    申请日:2001-10-08

    CPC classification number: G01R23/16

    Abstract: A spectrum analyzer that may be implemented by a simple microcontroller that does not have a hardware multiply function is disclosed. The spectrum analyzer of the present invention utilizes at least five frequency bins. The input signal is sampled at four times the bin frequency. The input signal is sampled at twice the Nyquist rate, which results in symmetries in the sin(wn) and cos(wn) functions. These symmetries allow the in-phase and quadrature components of the input signal to be calculated by add, ignore or subtract operations instead of the more complex multiplication and integration operations. Accordingly, the energy for each bin may be calculated with a minimum number of multiply operations. Because the number of multiply operations have been significantly reduced, these multiply operations may be performed by software instead of hardware. As a result, the spectrum analyzer may be implemented with a simple processor that does not have a hardware multiply. Another frequency bin is added by oversampling the highest frequency. A low pass filter is used to eliminate the effect of aliasing on the other frequency bins. A simple processor can still handle a bin that has been processed in this manner. As a result, at least five frequency bins may be processed by a spectrum analyzer implemented on a simple processor.

    Abstract translation: 公开了可以由不具有硬件乘法功能的简单微控制器实现的频谱分析仪。 本发明的频谱分析仪使用至少五个频率分
    组。 输入信号以四倍的频率采样。 输入信号以奈奎斯特速率的两倍采样,这导致sin(wn)和cos(wn)函数中的对称性。 这些对称性允许输入信号的同相和正交分量通过加法,忽略或减法运算而不是更复杂的乘法和积分运算来计算。 因此,可以用最小的乘法运算来计算每个仓的能量。 由于乘法运算的数量已经大大减少,所以这些乘法运算可以由软件代替硬件执行。 结果,频谱分析仪可以用不具有硬件乘法的简单处理器来实现。 通过过采样最高频率来添加另一个频率仓。 低通滤波器用于消除混叠对其他频率仓的影响。 一个简单的处理器仍然可以处理已经以这种方式处理的bin。 结果,至少五个频率仓可以由在简单处理器上实现的频谱分析仪处理。

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