公开(公告)号：US08139591B1

公开(公告)日：2012-03-20

申请号：US12874681

申请日：2010-09-02

Applicant: Deepak Goel ,  Ramesh Panwar

Inventor： Deepak Goel ,  Ramesh Panwar

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L45/56 ,  H04L45/742 ,  H04L45/7453

Abstract: In one embodiment, a method includes receiving a key associated with a portion of a data packet, comparing the key to a first range extreme, selecting a second range extreme, and comparing the key with the second range. The first range extreme is associated with a first range and the second range is associated with a second range. The second range is selected based on the comparing the key to the first range extreme. The method includes producing a policy vector associated with the first or second range.

Abstract translation: 在一个实施例中，一种方法包括接收与数据分组的一部分相关联的密钥，将密钥与第一范围极值进行比较，选择第二范围极值，以及将密钥与第二范围进行比较。 第一范围极值与第一范围相关联，并且第二范围与第二范围相关联。 基于比较键与第一范围极值选择第二范围。 该方法包括产生与第一或第二范围相关联的策略向量。

公开(公告)号：US20110134916A1

公开(公告)日：2011-06-09

申请号：US12794175

申请日：2010-06-04

Applicant: Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan

Inventor： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan

IPC: H04L12/56

CPC classification number: H04L45/745 ,  H04L49/1515 ,  H04L49/3009

Abstract: In one embodiment, an apparatus comprises a range selection module, a first stage of bloom filters, a second stage of bloom filters and a hashing module. The range selection module is configured to define a set of hash key vectors based on a set of range values associated with at least a portion of an address value from a data packet received at a multi-stage switch. The first stage of bloom filters and the second stage of bloom filters are collectively configured to determine that at least a portion of a hash key vector from the set of hash key vectors has a probability of being included in a hash table. The hashing module is configured to produce a hash value based on the hash key vector such that a first policy vector is selected based on the hash value and the first policy vector is decompressed to produce a second policy vector associated with the data packet.

Abstract translation: 在一个实施例中，一种装置包括范围选择模块，第一阶段的布隆过滤器，第二阶段的布隆过滤器和散列模块。 范围选择模块被配置为基于与在多级交换机处接收的数据分组的地址值的至少一部分相关联的一组范围值来定义一组散列密钥向量。 布隆过滤器的第一阶段和布隆过滤器的第二阶段共同配置为确定来自该组散列密钥向量的散列密钥向量的至少一部分具有被包括在散列表中的概率。 散列模块被配置为基于散列密钥向量产生散列值，使得基于散列值选择第一策略向量，并且解压缩第一策略向量以产生与数据分组相关联的第二策略向量。

公开(公告)号：US07889741B1

公开(公告)日：2011-02-15

申请号：US12347499

申请日：2008-12-31

Applicant: Ramesh Panwar ,  Deepak Goel ,  Jianhui Huang ,  Srinivasan Jagannadhan

Inventor： Ramesh Panwar ,  Deepak Goel ,  Jianhui Huang ,  Srinivasan Jagannadhan

IPC: H04L12/56 ,  H04L12/28 ,  G06F9/26

CPC classification number: H04L49/30

Abstract: In one embodiment, a method includes accessing a condition test vector, selecting a key from a plurality of keys, and determining whether the key selected and a condition value satisfy a condition relation. The accessing being based on an index value. The condition test vector including a first plurality of bit values defining the condition relation, a second plurality of bit values defining a key selector, and a third plurality of bit values defining the condition value. The selecting being based on the second plurality of bit values. Each key from the plurality of keys including a combination of bit values representing a portion of a data packet. A result is defined based on the determining.

Abstract translation: 在一个实施例中，一种方法包括访问条件测试向量，从多个键中选择密钥，以及确定所选择的密钥和条件值是否满足条件关系。 访问是基于索引值。 条件测试向量包括定义条件关系的第一多个比特值，定义密钥选择器的第二多个比特值以及定义条件值的第三多个比特值。 所述选择基于所述第二多个比特值。 来自多个键的每个键包括表示数据分组的一部分的比特值的组合。 结果是基于确定而定义的。

公开(公告)号：US07835357B2

公开(公告)日：2010-11-16

申请号：US12242172

申请日：2008-09-30

Applicant: Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

Inventor： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

IPC: H04L12/28

CPC classification number: H04L45/745 ,  H04L49/1515 ,  H04L49/503 ,  H04L69/22

Abstract: In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.

Abstract translation: 在一个实施例中，一种方法，包括基于在多级交换机处接收到的数据分组的第一部分产生第一策略向量。 该方法还包括基于不同于数据分组的第一部分的数据分组的第二部分产生第二策略向量。 基于至少第一策略向量和至少第二策略向量的组合来生成第三策略向量。 第三策略向量包括被配置为触发多级切换处的元素以处理数据分组的比特值的组合。

公开(公告)号：US07796541B1

公开(公告)日：2010-09-14

申请号：US12242125

申请日：2008-09-30

Applicant: Deepak Goel ,  Ramesh Panwar

Inventor： Deepak Goel ,  Ramesh Panwar

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L45/56 ,  H04L45/742 ,  H04L45/7453

Abstract: In one embodiment, a method includes receiving a key associated with a portion of a data packet, comparing the key to a first range extreme, selecting a second range extreme, and comparing the key with the second range. The first range extreme is associated with a first range and the second range is associated with a second range. The second range is selected based on the comparing the key to the first range extreme. The method includes producing a policy vector associated with the first or second range.

Abstract translation: 在一个实施例中，一种方法包括接收与数据分组的一部分相关联的密钥，将密钥与第一范围极值进行比较，选择第二范围极值，以及将密钥与第二范围进行比较。 第一范围极值与第一范围相关联，并且第二范围与第二范围相关联。 基于比较键与第一范围极值选择第二范围。 该方法包括产生与第一或第二范围相关联的策略向量。

公开(公告)号：US20080114887A1

公开(公告)日：2008-05-15

申请号：US11983135

申请日：2007-11-07

Applicant: Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Nazar Zaidi ,  Yen Lee ,  Chau Nguyen ,  John Phillips ,  Yuhong Zhou ,  Gregory Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

Inventor： Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Nazar Zaidi ,  Yen Lee ,  Chau Nguyen ,  John Phillips ,  Yuhong Zhou ,  Gregory Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

IPC: G06F15/16

CPC classification number: H04L47/125 ,  H04L29/06 ,  H04L63/0485

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract translation: 网络内容服务设备包括适于执行一组网络服务的一组计算元件; 以及耦合所述一组计算元件中的计算元件的交换结构。 该组网络服务包括防火墙保护，网络地址转换，互联网协议转发，带宽管理，安全套接字层操作，Web缓存，Web交换和虚拟专用网络。 在计算元件上可操作的代码实现了网络服务，并且在还包括至少一个输入/输出端口的刀片上提供计算元件。

公开(公告)号：US20060064508A1

公开(公告)日：2006-03-23

申请号：US10944271

申请日：2004-09-17

Applicant: Ramesh Panwar ,  Umesh Kasture

Inventor： Ramesh Panwar ,  Umesh Kasture

IPC: G06F15/16

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9026

Abstract: A system and method allocate memory by a network processor system in an off-chip DRAM. Upon initiation, an on-chip DRAM controller module creates a software structure that allocates blocks of memory locations in the DRAM as packet memory blocks. As a CPU, input/output module, and intrusion detection circuit read and write packets from the DRAM across a common bus, the DRAM controller module facilitates the rapid flow of packets in and out of the DRAM. FreeLists of packet buffer blocks are maintained by both the DRAM controller and the CPU for quick access in directing the flow of packets to available packet buffer blocks.

Abstract translation: 系统和方法通过片外DRAM中的网络处理器系统分配存储器。 在启动时，片上DRAM控制器模块创建一种将DRAM中的存储单元块分配为分组存储器块的软件结构。 作为CPU，输入/输出模块和入侵检测电路通过公共总线从DRAM读取和写入数据包，DRAM控制器模块有助于快速流入和流出DRAM。 分组缓冲区块的自由列表由DRAM控制器和CPU维护，用于在将数据包流传送到可用的分组缓冲区块时进行快速访问。

公开(公告)号：US06920542B2

公开(公告)日：2005-07-19

申请号：US10105979

申请日：2002-03-25

Applicant: Frederick Gruner ,  Robert Hathaway ,  Ramesh Panwar ,  Elango Ganesan ,  Nazar Zaidi

Inventor： Frederick Gruner ,  Robert Hathaway ,  Ramesh Panwar ,  Elango Ganesan ,  Nazar Zaidi

IPC: G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

CPC classification number: H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

Abstract: A compute engine's central processing unit is coupled to a coprocessor that includes application engines. The central processing unit initializes the coprocessor to perform an application, and the coprocessor initializes an application engine to perform the application. The application engine responds by carrying out the application. In performing some applications, the application engine accesses cache memory—obtaining a physical memory address that corresponds to a virtual address and providing the physical address to the cache memory. In some instances, the coprocessor employs multiple application engines to carry out an application. In one implementation, the application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Abstract translation: 计算引擎的中央处理单元耦合到包括应用引擎的协处理器。 中央处理单元初始化协处理器以执行应用，并且协处理器初始化应用引擎以执行应用。 应用程序引擎通过执行应用程序进行响应。 在执行某些应用程序时，应用程序引擎访问高速缓冲存储器 - 获得与虚拟地址相对应的物理内存地址，并将物理地址提供给高速缓冲存储器。 在一些情况下，协处理器采用多个应用引擎来执行应用。 在一个实现中，应用引擎促进不同的网络服务，包括但不限于：1）虚拟专用网; 2）安全套接字层处理; 3）网页缓存; 4）超文本标记语言压缩; 5）病毒检查; 6）防火墙支持; 和7）网页切换。

公开(公告)号：US06895477B2

公开(公告)日：2005-05-17

申请号：US10105972

申请日：2002-03-25

Applicant: David Hass ,  Frederick Gruner ,  Nazar Zaidi ,  Ramesh Panwar ,  Mark Vilas

Inventor： David Hass ,  Frederick Gruner ,  Nazar Zaidi ,  Ramesh Panwar ,  Mark Vilas

IPC: G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

CPC classification number: H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

Abstract: A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first processing cluster forwards a memory request to the snoop controller for access to a memory location. In response to the memory request, the snoop controller places a snoop request on the snoop ring—calling for a change in ownership of the requested memory location. A second processing cluster receives the snoop request on the snoop ring. The second processing cluster generates a response to the snoop request. If the second processing cluster owns the requested memory location, the second processing cluster modifies ownership status of the requested memory location.

Abstract translation: 系统包括多个处理集群和适于服务存储器请求的监听控制器。 窥探控制器和每个处理集群耦合到一个监听环。 第一个处理群集将存储器请求转发到窥探控制器以访问内存位置。 响应于存储器请求，窥探控制器在窥探环上发出窥探请求，呼叫所请求的存储器位置的所有权改变。 第二个处理集群在侦听环上接收到窥探请求。 第二个处理集群生成对窥探请求的响应。 如果第二处理集群拥有所请求的存储器位置，则第二处理集群修改所请求的存储器位置的所有权状态。

公开(公告)号：US06240502B1

公开(公告)日：2001-05-29

申请号：US08881145

申请日：1997-06-25

Applicant: Ramesh Panwar ,  Ricky C. Hetherington

Inventor： Ramesh Panwar ,  Ricky C. Hetherington

IPC: G06F938

CPC classification number: G06F9/3851 ,  G06F9/5011 ,  G06F2209/507

Abstract: A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.

Abstract translation: 用于动态地重新配置处理器的方法和装置涉及将处理器置于具有第一数量（m）股线的第一配置中，而编码指令包括数（m）个线程的指令。 每个m个线程中的指令在m个线之一上使用执行资源执行，其中至少一些在m个线之间共享。 虽然编码的指令包括来自数个（n）个线程的指令，但是处理器被置于具有第二数量（n）个线束的第二配置中。 使用执行资源在n个链中的每一个执行指令，其中至少一些在n个链​​之间共享。