公开(公告)号：US20120005679A1

公开(公告)日：2012-01-05

申请号：US13156492

申请日：2011-06-09

Applicant: Young Sam Shin ,  Seung Won Lee ,  Shi Hwa Lee ,  Suk Jin Kim ,  Min Young Son

Inventor： Young Sam Shin ,  Seung Won Lee ,  Shi Hwa Lee ,  Suk Jin Kim ,  Min Young Son

IPC: G06F9/46

CPC classification number: G06F11/3466 ,  G06F11/3423 ,  G06F2201/88

Abstract: Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.

Abstract translation: 提供了一种用于测量应用程序的性能或进展状态以便在使用微架构的计算环境中执行数据处理并执行特定功能的方法和装置。 线程进度跟踪装置可以包括：选择器，用于选择构成应用程序的至少一个线程; 确定单元，基于预定标准，确定指令执行方案是否对应于具有规则周期的确定性执行方案或具有相对于构成对应线程的至少一个指令中的每一个指令具有不规则延迟周期的非确定性执行方案 ; 以及确定性进度计数器，用于生成关于由确定性执行方案执行的指令的确定性进度索引，不包括由非确定性执行方案执行的指令。

公开(公告)号：US20110252258A1

公开(公告)日：2011-10-13

申请号：US12904782

申请日：2010-10-14

Applicant: Chae Seok IM ,  Shi Hwa LEE ,  Seung Won LEE ,  Jae Don LEE ,  Min Kyu JEONG

Inventor： Chae Seok IM ,  Shi Hwa LEE ,  Seung Won LEE ,  Jae Don LEE ,  Min Kyu JEONG

IPC: G06F1/32 ,  G06F12/00

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.

Abstract translation: 提供了一种有效处理多核同步的硬件加速装置，方法和计算机可读介质。 不能获取锁定变量的处理器核心可以切换到低功率睡眠模式，并且可能减少功率的浪费。 此外，当返回锁定变量时，可以将唤醒信号发送到以低功率睡眠模式操作的处理器核心，并且可以激活处理器核心。

公开(公告)号：US07996630B2

公开(公告)日：2011-08-09

申请号：US12805651

申请日：2010-08-11

Applicant: Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

Inventor： Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/45

CPC classification number: G06F8/4441

Abstract: Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location.

Abstract translation: 提供了一种在多处理器片上系统（MPSoC）中管理存储器的方法。 根据本发明的一个方面，通过基于存储器访问频率，参照符号表确定对应于符号的变量或函数的存储位置，可以反映存储器的局部性并且可以有效地使用受限的存储器资源 如果所确定的存储位置与先前存储位置不同，则将所确定的存储位置与先前存储位置进行比较，以及将存储在先前存储位置中的变量或功能复制到所确定的存储位置。

公开(公告)号：US20110101114A1

公开(公告)日：2011-05-05

申请号：US13006068

申请日：2011-01-13

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06K19/073

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US20110016285A1

公开(公告)日：2011-01-20

申请号：US12591946

申请日：2009-12-04

Applicant: Jae Don Lee ,  Shi Hwa Lee ,  Seung Won Lee ,  Chae Seok Im ,  Min Kyu Jeong

Inventor： Jae Don Lee ,  Shi Hwa Lee ,  Seung Won Lee ,  Chae Seok Im ,  Min Kyu Jeong

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/023 ,  G06F12/0292

Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.

Abstract translation: 公开了一种便笺本式存储器管理装置及其方法。 临时存储器管理装置将暂存器存储器划分为多个单位块，维持与主存储器中的多个单位块的索引相对应的存储器分配表，并管理暂存存储器。

公开(公告)号：US20100323799A1

公开(公告)日：2010-12-23

申请号：US12820984

申请日：2010-06-22

Applicant: Seung Won LEE ,  Koo MIN

Inventor： Seung Won LEE ,  Koo MIN

IPC: A63F9/24

CPC classification number: A63F13/60 ,  A63F13/12 ,  A63F13/52 ,  A63F2300/66 ,  H04L67/38

Abstract: An approach is provided for providing a service using an on-line game capable of, maximizing effects of services associated with the on-line game, and recording media recording a program for implementing the service providing method. The service providing method may include, for example, storing, in a rendering region, game object drawing information of a game screen for the on-line game in response to a request for reproducing the game screen; hooking the rendering region to change the game object drawing information so that service object information provided from a game server is included in the game object drawing information; storing the changed game object drawing information in the rendering region; and providing the game screen by rendering the game object drawing information including the service object information stored in the rendering region.

Abstract translation: 提供一种使用能够最大化与在线游戏相关联的服务的效果的在线游戏来提供服务的方法，以及记录用于实现服务提供方法的程序的记录媒体。 服务提供方法可以包括例如响应于再现游戏画面的请求在呈现区域中存储用于在线游戏的游戏画面的游戏对象绘图信息; 钩住渲染区域以改变游戏对象绘制信息，使得从游戏服务器提供的服务对象信息被包括在游戏对象绘图信息中; 将改变的游戏对象绘图信息存储在呈现区域中; 以及通过渲染包括存储在呈现区域中的服务对象信息的游戏对象绘图信息来提供游戏画面。

公开(公告)号：US20100312977A1

公开(公告)日：2010-12-09

申请号：US12805651

申请日：2010-08-11

Applicant: Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

Inventor： Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/16

CPC classification number: G06F8/4441

Abstract: Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location.

Abstract translation: 提供了一种在多处理器片上系统（MPSoC）中管理存储器的方法。 根据本发明的一个方面，通过基于存储器访问频率，参照符号表确定对应于符号的变量或函数的存储位置，可以反映存储器的局部性并且可以有效地使用受限的存储器资源 如果所确定的存储位置与先前存储位置不同，则将所确定的存储位置与先前存储位置进行比较，以及将存储在先前存储位置中的变量或功能复制到所确定的存储位置。

公开(公告)号：US07805582B2

公开(公告)日：2010-09-28

申请号：US11898659

申请日：2007-09-13

Applicant: Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

Inventor： Keun Soo Yim ,  Jeong-joon Yoo ,  Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jae-don Lee ,  Min-kyu Jeong

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F9/45

CPC classification number: G06F8/4441

Abstract: Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location.

公开(公告)号：US20100146168A1

公开(公告)日：2010-06-10

申请号：US12453514

申请日：2009-05-13

Applicant: Young Sam Shin ,  Seung Won Lee

Inventor： Young Sam Shin ,  Seung Won Lee

IPC: G06F13/00

CPC classification number: G06F13/102

Abstract: A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port.

Abstract translation: 一种使用软件总线的组件之间的相互连接的方法，其可以分析其中至少一个组件彼此连接的端口是否是根据端口的应用的数据传输端口或功能接口呼叫端口， 根据分析结果确定端口的执行属性，并根据端口的执行属性来控制端口。 功能接口调用端口可以使用按需功能调用端口的属性或使用加载功能调用端口的属性的递归服务器连接端口将每个请求划分为线程生成连接端口中的任何一个 根据被叫端口的类型。

公开(公告)号：US20100124123A1

公开(公告)日：2010-05-20

申请号：US12619227

申请日：2009-11-16

Applicant: Seung Won Lee

Inventor： Seung Won Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3454 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a sense amplifier circuit sensing first data from a memory cell via a bit line and outputting the sensed first data, in response to a read command. A write driver circuit programs the memory cell and stores second data indicating a programming state of the memory cell, in response to a program command. A verification block outputs a result of a comparison between the first and second data in response to a first read command. The second data is updated based on the determination on the programming of the memory cell in response to a second read command applied following the first read command.

Abstract translation: 非易失性存储器件包括：读出放大器电路，响应于读取命令，经由位线检测来自存储器单元的第一数据并输出所感测的第一数据。 写入驱动器电路响应于程序命令编程存储器单元并存储指示存储器单元的编程状态的第二数据。 验证块响应于第一读取命令输出第一和第二数据之间的比较结果。 响应于在第一读取命令之后应用的第二读取命令，基于对存储器单元的编程的确定来更新第二数据。