公开(公告)号：US11381514B2

公开(公告)日：2022-07-05

申请号：US15973153

申请日：2018-05-07

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Cahya Adiansyah Masputra

IPC: H04L47/62 ,  H04L45/30

Abstract: Methods and apparatus for non-sequential packet transfer. Prior art multi-processor devices implement a complete network communications stack at each processor. The disclosed embodiments provide techniques for delivering network layer (L3) and/or transport layer (L4) data payloads in the order of receipt, rather than according to the data link layer (L2) order. The described techniques enable e.g., earlier packet delivery. Such design topologies can operate within a substantially smaller memory footprint compared to prior art solutions. As a related benefit, applications that are unaffected by data link layer corruptions can receive data immediately (rather than waiting for the re-transmission of an unrelated L4 data flow) and thus the overall network latency can be greatly reduced and user experience can be improved.

公开(公告)号：US20210041908A1

公开(公告)日：2021-02-11

申请号：US17066321

申请日：2020-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F1/12 ,  G06F1/324

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

公开(公告)号：US20210011785A1

公开(公告)日：2021-01-14

申请号：US17035499

申请日：2020-09-28

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/46

Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

公开(公告)号：US10853272B2

公开(公告)日：2020-12-01

申请号：US16259543

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20200348989A1

公开(公告)日：2020-11-05

申请号：US16933826

申请日：2020-07-20

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US10775871B2

公开(公告)日：2020-09-15

申请号：US15647063

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/3287 ,  G06F9/4401

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20200210224A1

公开(公告)日：2020-07-02

申请号：US16813407

申请日：2020-03-09

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav V. Petkov

IPC: G06F9/46 ,  G06F9/54

Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

公开(公告)号：US10591976B2

公开(公告)日：2020-03-17

申请号：US15647103

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US10585699B2

公开(公告)日：2020-03-10

申请号：US16049624

申请日：2018-07-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav V. Petkov

IPC: G06F9/46 ,  G06F9/54

Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

公开(公告)号：US20200065244A1

公开(公告)日：2020-02-27

申请号：US16112480

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Jason McElrath

IPC: G06F12/084 ,  G06F13/16

Abstract: Methods and apparatus for using and controlling a jointly shared memory-mapped region between multiple processors in a pass-through manner. Existing data pipe input/output (I/O) techniques for mobile device operation enable high speed data transfers, decoupled independent operation of processors, reduced software complexity, reduced power consumption, etc. However, legacy functions and capabilities may only receive marginal benefits from data pipe I/O operation, and in some cases, may even suffer adverse effects from e.g., processing overhead and/or context switching. The present disclosure is directed to dynamically isolating and reaping back a jointly shared memory space for data transfer in a “pass through” manner which does not require kernel space intervention. More directly, a jointly shared region of host memory is accessible to both the peripheral client and the host client in user space.