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公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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公开(公告)号：US07822099B2
公开(公告)日：2010-10-26
申请号：US11758975
申请日：2007-06-06
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j or s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
摘要翻译： 高斯噪声由离散模拟ri，j模拟。 选择第一参数α和多个第一和第二整数i和j。 识别多个点i，j，并且基于α，i和j针对每个点计算幅度si，j。 离散的模拟ri，j基于相应的si，j。 给出α= 2 B-A 2 B和D> i≥0和2C>j≥0的实例，其中B≥0,2B> A> 0，C≥1和D≥1，并且幅度si，j = 1-αi +αi·1-α2 C·j·肯·杜·斯D-1，j = 1-αD-1 +αD·1·1 2 C·j。 在一些实施例中，基于α和i定义段。 根据j的相应值将该段划分成点，并且对该段的每个点计算大小。 对于i的每个值迭代地重复定义和分割段并计算幅度。
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公开(公告)号：US07548844B2
公开(公告)日：2009-06-16
申请号：US11706943
申请日：2007-02-13
IPC分类号： G06F9/45
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
摘要翻译： 本发明涉及一种用于最长前缀搜索引擎的顺序测试器。 测试器可以包括最长的前缀搜索引擎，用于向最长的前缀搜索引擎提供几乎随机的输入命令的输入生成器，并输出可以表示最长前缀搜索引擎的搜索表的浮动矩形，编码模块 用于向最长前缀搜索引擎提供地址和前缀信息，用于向最长前缀搜索引擎提供数据信息的映射模块，用于执行超级搜索操作的超级搜索引擎和用于计算最长前缀搜索引擎的预测输出的分析器 并将预测输出与由最长前缀搜索引擎计算的实际输出进行比较。
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64.发明授权Method and system for outputting a sequence of commands and data described by a flowchart 有权用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 该方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。 。 。 xN，并输出命令和数据的顺序。
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公开(公告)号：US07430694B2
公开(公告)日：2008-09-30
申请号：US11038698
申请日：2005-01-20
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译： 本发明提供了一种用于切片的存储器BISR架构。 该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。 。 ，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关 模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。
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66.发明授权Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效用于通过具有优化的数量和/或开关的逻辑电路来评估逻辑功能的方法公开(公告)号：US07328423B2
公开(公告)日：2008-02-05
申请号：US11055752
申请日：2005-02-10
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.
摘要翻译： 一种用于创建具有优化数量的AND / OR开关的逻辑电路的方法，其评估在高级描述中定义的逻辑功能。 通过分析用于定义逻辑功能的运算符之间的依赖关系，本发明可以简化用于定义逻辑功能的高级描述中使用的功能步骤，从而创建具有优化数量的AND / OR开关的逻辑电路。
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公开(公告)号：US07328382B2
公开(公告)日：2008-02-05
申请号：US11270077
申请日：2005-11-09
CPC分类号： G11C29/44 , G06F11/00 , G11C29/4401 , G11C29/72
摘要： The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller. The BISR_IN input port is connected to data input of a first flip-flop, and output of a K-th flip-flop is connected to input of a (K+1)-th flip-flop, K=1, 2, . . . , N-1. When at least one of the N memory instances is defective, the memory BISR controller may reconfigure connections among the N memory instances to use other memory instance(s) instead of the defective memory instance(s).
摘要翻译： 本发明提供了一种用于连接到N个存储器实例的存储器内置自修复（BISR）控制器的架构，其中N是大于1的正整数。该架构包括N组数据端口，N个BISR_SUBMOD模块用于连接到 N个内存实例，以及用于设置内存BISR控制器配置的CLK_IN输入端口和BISR_IN输入端口。 N组数据端口中的每一个包括（1）用于连接到相应存储器实例的输入的PHY_IN输出端口; （2）用于连接到相应存储器实例的输出的PHY_OUT输入端口; （3）用于向相应的存储器实例发送信号的LOG_IN输入端口; 和（4）用于从相应的存储器实例接收信号的LOG_OUT输出端口。 N BISR_SUBMOD模块中的每一个包括触发器，第一多路复用器和第二复用器。 CLK_IN输入端口连接到存储器BISR控制器的所有N个触发器的时钟输入。 BISR_IN输入端口连接到第一触发器的数据输入，第K触发器的输出连接到第（K + 1）个触发器的输入，K = 1,2。 。 。 ，N-1。 当N个存储器实例中的至少一个存在缺陷时，存储器BISR控制器可以重新配置N个存储器实例之间的连接以使用其他存储器实例而不是缺陷存储器实例。
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公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译： 本发明提供了一种RRAM拼接网表的验证方法。 该方法可以包括以下步骤。 属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。 对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。 。 。 ，N.
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69.发明授权System and method for efficiently testing a large random access memory space 失效用于有效测试大型随机存取存储空间的系统和方法公开(公告)号：US07305597B1
公开(公告)日：2007-12-04
申请号：US10646535
申请日：2003-08-22
CPC分类号： G11C29/26 , G11C29/1201 , G11C29/40 , G11C2029/2602 , G11C2029/3602
摘要： A system for, and method of, allowing conventional memory test circuitry to test parallel memory arrays and an integrated circuit incorporating the system or the method. In one embodiment, the system includes: (1) bit pattern distribution circuitry that causes a probe bit pattern generated by the memory test circuitry to be written to each of the memory arrays, (2) a pseudo-memory, coupled to the bit pattern distribution circuitry, that receives a portion of the probe bit pattern and (3) combinatorial logic, coupled to the pseudo-memory, that employs the portion and data-out bit patterns read from the memory arrays to generate a response bit pattern that matches the probe bit pattern only if all of the data-out bit patterns match the probe bit pattern.
摘要翻译： 用于允许传统的存储器测试电路测试并行存储器阵列的系统和方法以及结合该系统或方法的集成电路。 在一个实施例中，系统包括：（1）位图模式分配电路，其使得存储器测试电路产生的探针位模式被写入每个存储器阵列，（2）耦合到位模式的伪存储器 分配电路，其接收探针位模式的一部分和（3）耦合到伪存储器的组合逻辑，其采用从存储器阵列读取的部分和数据输出位模式，以产生与存储器阵列匹配的响应位模式 探针位模式只有当所有数据输出位模式与探头位模式匹配时。
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公开(公告)号：US07257807B2
公开(公告)日：2007-08-14
申请号：US10667812
申请日：2003-09-22
摘要： The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses. Moreover, when the processor integrated circuit executes a parallel processor command, the processor integrated circuit executes all subcommands included in the parallel processor command in parallel in one clock cycle.
摘要翻译： 本发明涉及并行处理器语言，用于将C ++程序转换为并行处理器语言的方法以及用于优化并行处理器程序的执行时间的方法。 在本发明的示例性方面，用于定义处理器集成电路的并行处理器程序包括具有地址的多个处理器命令。 多个处理器命令可以包括起始处理器命令，并且多个处理器命令中的每一个包括一个或多个子命令。 当处理器集成电路执行并行处理器程序时，处理器集成电路首先执行起始处理器命令，然后基于地址的顺序执行多个处理器命令中的其余部分。 此外，当处理器集成电路执行并行处理器命令时，处理器集成电路在一个时钟周期内并行地执行并行处理器命令中包括的所有子命令。
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