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    INTERFACE MECHANISM FOR QUICKLY ACCESSING RECENTLY USED ARTIFACTS IN A COMPUTER DESKTOP ENVIRONMENT
    63.
    发明申请
    INTERFACE MECHANISM FOR QUICKLY ACCESSING RECENTLY USED ARTIFACTS IN A COMPUTER DESKTOP ENVIRONMENT 审中-公开
    用于在计算机桌面环境中快速访问最近使用的艺术品的界面机制

    公开(公告)号：US20080005685A1

    公开(公告)日：2008-01-03

    申请号：US11427965

    申请日：2006-06-30

    申请人： Clemens Drews ,  James Lin ,  Michael Muller ,  Andrew L. Schirmer ,  John C. Tang

    发明人： Clemens Drews ,  James Lin ,  Michael Muller ,  Andrew L. Schirmer ,  John C. Tang

    IPC分类号： G06F9/00

    CPC分类号： G06F3/0481

    摘要： Interface mechanism for quickly accessing recently used artifacts in a computer desktop environment. The interface mechanism integrates across a multitude of tools available in a computer desktop environment to present a list of recently used computer artifacts that can be automatically sorted or filtered in useful ways. Examples of computer-based artifacts that the interface can present include objects that relate to people, events, URLs, email messages, attachments, shared objects or shared activities. Filtering and sorting operations enable the interface mechanism to provide a list of the computer artifacts in a manner that is useful to the user. Also, the interface mechanism permits to perform frequently desired operations beyond opening a file or application such as dragging and dropping items for copying and pasting into the user's current context.

    摘要翻译： 用于在计算机桌面环境中快速访问最近使用的工件的接口机制。 接口机制集成在计算机桌面环境中可用的多种工具中，以呈现最近使用的计算机工件的列表，可以以有用的方式自动排序或过滤。 接口可以呈现的基于计算机的工件的示例包括与人，事件，URL，电子邮件消息，附件，共享对象或共享活动相关的对象。 过滤和排序操作使接口机制能够以对用户有用的方式提供计算机工件的列表。 此外，接口机制允许执行经常期望的操作，除了打开文件或应用程序，例如拖放用于复制和粘贴到用户当前上下文中的项目。

    Cushioning system for footwear
    65.
    发明申请
    Cushioning system for footwear 审中-公开
    鞋类缓冲系统

    公开(公告)号：US20070113425A1

    公开(公告)日：2007-05-24

    申请号：US11286187

    申请日：2005-11-23

    申请人： Gary Wakley ,  James Lin ,  Thomas Gray ,  Steve Davis

    发明人： Gary Wakley ,  James Lin ,  Thomas Gray ,  Steve Davis

    IPC分类号： A43B13/18 ,  A43B13/20 ,  A43B13/12

    CPC分类号： A43B13/20

    摘要： A midsole for footwear includes at least one solid or hollow cushioning tube positioned therein for improving the cushioning of the midsole. Preferably, the midsole includes a plurality of cushioning tubes fabricated of an elastomeric material. The tubes may vary in diameter and/or wall thickness relative to one another for varying the cushioning and stability characteristics of the system. Each tube may also vary in diameter and/or wall thickness along its length.

    摘要翻译： 用于鞋类的中底包括至少一个位于其中的固体或中空缓冲管，用于改善中底的缓冲。 优选地，中底包括由弹性体材料制成的多个缓冲管。 管可以相对于彼此改变直径和/或壁厚，以改变系统的缓冲和稳定性特征。 每个管也可以沿其长度改变直径和/或壁厚。

    Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits
    67.
    发明授权
    Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits 有权
    用于集成电路双镶嵌后端中蚀刻阻挡层的低介电常数电介质

    公开(公告)号：US06498399B2

    公开(公告)日：2002-12-24

    申请号：US09391721

    申请日：1999-09-08

    申请人： Henry Chung ,  James Lin

    发明人： Henry Chung ,  James Lin

    IPC分类号： H01L23485

    CPC分类号： H01L21/76835 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829

    摘要： The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material. At least one via extends through the first dielectric material layer and the second dielectric material layer, and at least one trench extends through the additional layer of the first dielectric material to the via. A lining of a barrier metal is formed on inside walls and a floor of the trench and on inside walls and a floor the via. A fill metal fills the trench and via in contact with the lining of the barrier metal.

    摘要翻译： 本发明提供了诸如集成电路器件的微电子器件。 这样具有通孔，互连金属化和使用不同的低介电常数金属间电介质的布线。 由于两种电介质的等离子体蚀刻特性明显不同，因此使用有机和无机低k电介质都有优势。 一个电介质用作蚀刻其它电介质的蚀刻步骤，因此不需要额外的蚀刻阻挡层。 形成具有衬底和位于衬底上的第一介电材料层的微电子器件。 第二电介质材料层位于第一电介质层上，第一电介质材料的另一层位于第二电介质材料上。 至少一个通孔延伸穿过第一介电材料层和第二介电材料层，并且至少一个沟槽延伸穿过第一介电材料的附加层到通孔。 阻挡金属的衬里形成在内壁和沟槽的地板以及内壁和地板上的通孔上。 填充金属填充与阻挡金属的衬里接触的沟槽和通孔。

    Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics
    68.
    发明授权
    Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics 失效
    具有多个低介电常数的金属间电介质的集成电路的制造方法

    公开(公告)号：US06383912B1

    公开(公告)日：2002-05-07

    申请号：US09694194

    申请日：2000-10-23

    申请人： Henry Chung ,  James Lin

    发明人： Henry Chung ,  James Lin

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76835 ,  H01L2221/1031

    摘要： The invention provides process for producing microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer. Either a sacrificial metal layer or and an additional layer the first dielectric material is positioned on the second dielectric material. At least one via extends through the first dielectric material layer and at least one trench extends through the additional layer of the first dielectric material and the second dielectric material layer to the via. A lining of a barrier metal is formed on inside walls and a floor of the trench and on inside walls and a floor the via. A fill metal fills the trench and via in contact with the lining of the barrier metal.

    摘要翻译： 本发明提供了用于制造诸如集成电路器件的微电子器件的方法。 这样具有通孔，互连金属化和使用不同的低介电常数金属间电介质的布线。 由于两种电介质的等离子体蚀刻特性明显不同，因此使用有机和无机低k电介质都有优势。 一个电介质用作蚀刻其它电介质的蚀刻步骤，因此不需要额外的蚀刻阻挡层。 形成具有衬底和位于衬底上的第一介电材料层的微电子器件。 第二电介质材料层位于第一电介质层上。 牺牲金属层或附加层中的第一介电材料位于第二电介质材料上。 至少一个通孔延伸穿过第一介电材料层，并且至少一个沟槽延伸穿过第一介电材料的附加层和第二介电材料层延伸至通孔。 阻挡金属的衬里形成在内壁和沟槽的地板以及内壁和地板上的通孔上。 填充金属填充与阻挡金属的衬里接触的沟槽和通孔。

    Female computer connector
    69.
    发明授权
    Female computer connector 失效
    母电脑连接器

    公开(公告)号：US5228874A

    公开(公告)日：1993-07-20

    申请号：US944956

    申请日：1992-09-15

    申请人： James Lin

    发明人： James Lin

    IPC分类号： H01R13/502 ,  H01R13/504

    CPC分类号： H01R13/504 ,  H01R24/76 ,  H01R13/502 ,  H01R2107/00 ,  H01R2201/04 ,  H01R2201/06

    摘要： A female computer connector includes a flat insert connected to a housing to hold a set of receptacles therein and molded with an outer shell through the process of injection molding, wherein the housing has elongated ribs inserted into gaps on a front edge of the flat insert to separate the receptacles; the receptacles each has two projections respectively hooked in two spaced recessed retaining surface portions on a respective channel on the flat insert for positioning, and a rear end formed into two side wings pinched to bind up a respective conductor.

    摘要翻译： 母电脑连接器包括连接到壳体的平坦插入件，用于将一组容器保持在其中并通过注射成型过程用外壳模制，其中壳体具有插入到平坦插入件的前边缘上的间隙中的细长肋条 分开容器; 插座每个具有分别钩在平面插入件上的相应通道上的两个间隔开的凹入保持表面部分中的两个突起，用于定位，并且后端形成为夹紧相应导体的两个侧翼。