公开(公告)号：US06791149B2

公开(公告)日：2004-09-14

申请号：US10287569

申请日：2002-11-04

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L2976

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L23/485 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.

Abstract translation: 提供了扩散阻挡膜层及其制造和使用方法。 这些膜包括掺杂硼的TiCl 4基氮化钛，并且提供具有良好粘合剂，导电性和抗扩散性能的改进的扩散阻挡层。 这些膜可以形成在硅衬底上，而没有诸如TiSix的下面的接触层，对于浅接点的接触和集成电路的其它微型部件的制造的改进。

公开(公告)号：US06731063B2

公开(公告)日：2004-05-04

申请号：US10266969

申请日：2002-10-07

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J1304

CPC classification number: H01J9/025

Abstract: A field emission array includes a dielectric structure with at least two dielectric layers between the cathode and anode grid thereof. The lower dielectric layer is planarized to minimize the occurrence of electrical shorts between the cathode and anode grid of the field emission array. Thus, the upper dielectric layer is substantially free of any electrically conductive defects or imperfections that extend through the lower dielectric layer. In addition, the field emission array includes an array of emitter tips, which are laterally surrounded and may be spaced apart from the dielectric structure. The field emission array may also include a grid over the dielectric structure and the emitter tips, with the emitter tips being exposed through grid openings or apertures.

Abstract translation: 场致发射阵列包括在其阴极和阳极栅格之间具有至少两个电介质层的电介质结构。 平坦化下部电介质层以最小化场发射阵列的阴极和阳极栅极之间的电短路的发生。 因此，上电介质层基本上没有延伸穿过下电介质层的任何导电缺陷或缺陷。 此外，场发射阵列包括发射极尖端的阵列，其被横向包围并且可以与电介质结构间隔开。 场发射阵列还可以包括电介质结构上的栅极和发射极尖端，发射极尖端通过栅格开口或孔暴露。

公开(公告)号：US06696368B2

公开(公告)日：2004-02-24

申请号：US09918919

申请日：2001-07-31

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L2131

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract translation: 提供半导体结构中的导电接触，以及形成导电部件的方法。 触点可用于在诸如存储器件的集成电路中的绝缘层下方的有源部件提供电连接。 导电触点包括硼掺杂的TiCl 4基氮化钛，并且具有与绝缘层的足够水平的粘合性，以便当形成为大于约200埃的厚度时，消除从接触开口的侧壁的剥离和绝缘层的破裂 。

公开(公告)号：US06586285B1

公开(公告)日：2003-07-01

申请号：US10094017

申请日：2002-03-06

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: H01L2184

CPC classification number: C23C16/4407 ,  C23C16/14 ,  C23C16/42 ,  C23C16/4404

Abstract: A first cleaning is conducted on a plasma enhanced chemical vapor deposition chamber at room ambient pressure. After the first cleaning, elemental titanium comprising layers are chemical vapor deposited on a first plurality of substrates within the chamber using at least TiCl4. Thereafter, titanium silicide comprising layers are plasma enhanced chemical vapor deposited on a second plurality of substrates within the chamber using at least TiCl4 and a silane. Thereafter, a second cleaning is conducted on the chamber at ambient room pressure. In one implementation after the first cleaning, an elemental titanium comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber. In another implementation, a titanium silicide comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber.

Abstract translation: 在室内环境压力下，在等离子体增强化学气相沉积室上进行第一次清洗。 在第一次清洁之后，使用至少TiCl 4，在室内的第一组多个衬底上化学气相沉积包含层的元素钛。 此后，包含层的硅化钛是使用至少TiCl 4和硅烷沉积在室内的第二多个基板上的等离子体增强化学气相。 此后，在室内在室内进行第二清洗。 在第一次清洁之后的一个实施方案中，元素钛包含层在室的内表面上化学气相沉积，而在室内没有接收半导体衬底。 在另一个实施方案中，包含硅化钛的层在室的内表面上化学气相沉积，而在腔室内不接收半导体衬底。

公开(公告)号：US06579140B2

公开(公告)日：2003-06-17

申请号：US10200849

申请日：2002-07-22

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J900

CPC classification number: H01J9/025

Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.

公开(公告)号：US06559581B2

公开(公告)日：2003-05-06

申请号：US10108973

申请日：2002-03-28

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J130

CPC classification number: H01J9/025

Abstract: A method of fabricating row lines and pixel openings of a field emission array. The method employs only two masks. A first mask employed in the method includes apertures alignable between rows of pixels of the field emission array. Electrically conductive material and semiconductive material exposed through the apertures are removed to define the row lines of the field emission array. A passivation layer is then disposed over at least selected portions of the field emission array. Then a second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer of the field emission array. Passivation material exposed through the apertures of the second mask is removed to define openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may then be removed to expose the underlying semiconductive grid and to further define the pixel openings.

Abstract translation: 一种制造场发射阵列的行线和像素开口的方法。 该方法仅使用两个掩模。 在该方法中采用的第一掩模包括可以在场发射阵列的像素行之间对准的孔。 通过孔径暴露的导电材料和半导体材料被去除以限定场致发射阵列的行线。 然后将钝化层设置在场致发射阵列的至少选定部分上。 然后，在场致发射阵列的钝化层上方设置包括可在场发射阵列的像素区域上对准的孔的第二掩模。 通过第二掩模的孔暴露的钝化材料被去除以限定穿过钝化层的开口和场致发射阵列的像素区域。 然后可以移除通过第二掩模的孔暴露的导电材料以暴露下面的半导电栅格并进一步限定像素开口。

公开(公告)号：US06498425B1

公开(公告)日：2002-12-24

申请号：US09667141

申请日：2000-09-21

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J1312

CPC classification number: H01J9/025

Abstract: A field emission array includes a dielectric structure with at least two dielectric layers between the cathode and anode grid thereof. The lower dielectric layer is planarized to minimize the occurrence of electrical shorts between the cathode and anode grid of the field emission array. Thus, the upper dielectric layer is substantially free of any electrically conductive defects or imperfections that extend through the lower dielectric layer. In addition, the field emission array includes an array of emitter tips, which are laterally surrounded and may be spaced apart from the dielectric structure. The field emission array may also include a grid over the dielectric structure and the emitter tips, with the emitter tips being exposed through grid openings or apertures.

Abstract translation: 场致发射阵列包括在其阴极和阳极栅格之间具有至少两个电介质层的电介质结构。 平坦化下部电介质层以最小化场发射阵列的阴极和阳极栅极之间的电短路的发生。 因此，上电介质层基本上没有延伸穿过下电介质层的任何导电缺陷或缺陷。 此外，场发射阵列包括发射极尖端的阵列，其被横向包围并且可以与电介质结构间隔开。 场发射阵列还可以包括电介质结构上的栅极和发射极尖端，发射极尖端通过栅格开口或孔暴露。

公开(公告)号：US06398609B2

公开(公告)日：2002-06-04

申请号：US09847926

申请日：2001-05-03

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J902

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines. The mask material may be removed and the layer of semiconductive material or conductive material planarized. A mask is disposed over the field emission array and portions of the layer of semiconductive material or conductive material removed therethrough to define emitter tips and their corresponding resistors. The substantially longitudinal center portion of each of the conductive lines may be removed to electrically isolate adjacent columns of pixels of the field emission array from each other. Field emission arrays fabricated by the method of the present invention are also within the scope of the present invention.

Abstract translation: 一种制造场致发射阵列的方法，其使用单个掩模来限定其发射极尖端及其对应的电阻器。 导电材料层设置在场致发射阵列的衬底上。 多个基本相互平行的导电线由导电材料层限定。 至少一层半导体材料或导电材料设置在导电线之上和暴露在相邻导电线之间的衬底的区域之上。 掩模材料设置在半导体材料或导电材料层上，基本上在每条导电线上方。 通过掩模材料暴露的半导体材料或导电材料层的部分可以被去除以暴露导电线的基本上纵向的中心部分。 半导体材料或导电材料层的其它部分可以保留在导电线的外围横向边缘上。 可以去除掩模材料并将半导体材料或导电材料层平坦化。 掩模设置在场发射阵列之上，半导体材料或导电材料层的部分通过其去除以限定发射极尖端及其对应的电阻器。 每个导线的基本上纵向的中心部分可被去除以将场发射阵列的相邻列彼此电隔离。 通过本发明的方法制造的场发射阵列也在本发明的范围内。

公开(公告)号：US06369497B1

公开(公告)日：2002-04-09

申请号：US09260405

申请日：1999-03-01

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J130

CPC classification number: H01J9/025

Abstract: A method of fabricating row lines and pixel openings of a field emission array. The method employs only two masks. A first mask employed in the method includes apertures alignable between rows of pixels of the field emission array. Electrically conductive material and semiconductive material exposed through the apertures are removed to define the row lines of the field emission array. A passivation layer is then disposed over at least selected portions of the field emission array. Then a second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer of the field emission array. Passivation material exposed through the apertures of the second mask is removed to define openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may then be removed to expose the underlying semiconductive grid and to further define the pixel openings.

公开(公告)号：US06326222B2

公开(公告)日：2001-12-04

申请号：US09819298

申请日：2001-03-27

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.

Abstract translation: 用于制造场发射阵列的方法使用单个掩模来限定发射极尖端，它们相应的电阻器，以及可选地导电线路。 将限定发射极尖端和电阻器的一个或多个材料层形成在基本上平行的导线上方和侧向相邻。 发射极尖端和电阻器材料或材料的层的暴露表面可以被平坦化。 然后定义发射极尖端和底层电阻。 导线的基本上纵向的中心部分可以在相邻的发射极尖端之间露出，每个导线的至少一个侧边缘部分被形成发射极尖端和电阻器后的材料所屏蔽。 可以去除导线的暴露部分以便限定导电迹线。 还公开了通过这种方法制造的场发射阵列和显示装置。