公开(公告)号：US5998260A

公开(公告)日：1999-12-07

申请号：US55685

申请日：1998-04-06

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for forming a DRAM capacitor that uses a sacrificial layer to form a gear-teeth mold for producing a storage electrode having a highly increased surface area. The mold in a sacrificial layer is formed by first depositing alternating layers of two different insulating materials on a dielectric layer, and then patterning the sacrificial layer to form an opening using a conventional method. Next, a wet etching operation is performed using an etchant having a high etching selectivity between the two insulating layers. Hence, sunken slots are formed in the insulating layers that have a higher etching rate than its adjacent insulating layers, thus obtaining a gear teeth cross-sectional profile. Finally, the mold in the sacrificial layer is used for forming the storage electrode.

Abstract translation: 一种用于形成DRAM电容器的方法，所述DRAM电容器使用牺牲层来形成具有高度增加的表面积的存储电极的齿轮齿模具。 牺牲层中的模具通过首先在介电层上沉积两种不同绝缘材料的交替层而形成，然后使用常规方法图案化牺牲层以形成开口。 接下来，使用在两个绝缘层之间具有高蚀刻选择性的蚀刻剂进行湿蚀刻操作。 因此，在具有比其相邻的绝缘层更高的蚀刻速率的绝缘层中形成凹槽，从而获得齿轮的横截面轮廓。 最后，牺牲层中的模具用于形成存储电极。

公开(公告)号：US5908314A

公开(公告)日：1999-06-01

申请号：US828428

申请日：1997-03-28

Applicant: Benjamin Szu-Min Lin ,  Chun-Cho Chen

Inventor： Benjamin Szu-Min Lin ,  Chun-Cho Chen

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/335

CPC classification number: H01L29/66507 ,  H01L21/28052

Abstract: A two-step metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on the gates. A first high-temperature process is executed to form a first metal salicide layer on the gates. A second metal layer is formed on the first metal salicide layer, sources (drains), spacers, and field oxides. A second high-temperature process is executed to form a thicker second metal salicide layer on the gates and a third metal salicide layer on the sources (drains). A wet etching is then performed. A dielectric layer is formded over the semiconductor substrate wherein the horizontal line of the dielectric layer is above the second metal salicide layer. Polishing is then performed. Finally, shallow contact windows and deep contact windows are then formed for the gates and sources (drains), respectively.

Abstract translation: 一种两步金属硅化物半导体工艺，适用于其上形成栅极，源极（漏极），间隔物和场氧化物的半导体衬底。 在栅极上形成第一金属层。 执行第一高温处理以在门上形成第一金属自对准硅化物层。 在第一金属硅化物层，源（漏极），间隔物和场氧化物上形成第二金属层。 执行第二高温处理以在栅极上形成较厚的第二金属硅化物层，并在源极（漏极）上形成第三金属硅化物层。 然后进行湿蚀刻。 介电层形成在半导体衬底上，其中电介质层的水平线在第二金属硅化物层之上。 然后执行抛光。 最后，分别为门和源（排水）形成浅接触窗和深接触窗。

公开(公告)号：US5854124A

公开(公告)日：1998-12-29

申请号：US881775

申请日：1997-06-24

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/76834 ,  Y10S438/97 ,  Y10S438/976

Abstract: A method for opening contacts of different depths in a semiconductor wafer after salicide processing. A sacrificial layer is formed over the wafer wherein the wafer further includes a first silicide layer and a second silicide layer formed thereon. The sacrificial layer is selectively removed such that only a portion of the sacrificial layer remains on the first silicide layer. An interlayer dielectric layer is formed over the wafer. The interlayer dielectric layer is planed. Contact windows are patterned. Contacts are opened to reveal the first silicide layer and the second silicide layer as contacts wherein the position where the first silicide layer is formed is higher than that where the second silicide layer is formed. Further, the thickness Y of the sacrificial layer is determined according to the following relation: Y=.DELTA.X.times.R.sub.SAC /(R.sub.ILD -R.sub.SAC), wherein .DELTA.X is the height difference between the first silicide layer and the second silicide layer, and R.sub.SAC and R.sub.ILD are the etching rates of the sacrificial layer and the interlayer dielectric layer while being etched by the same etching matter respectively. Using the sacrificial layer prevents the contacts of shallower depths from being over etched and consequently the resistance of contacts in the shallower windows will not be increased abnormally due to being over etched.

Abstract translation: 一种在自对准硅化物处理之后在半导体晶片中打开不同深度的触点的方法。 牺牲层形成在晶片上，其中晶片还包括形成在其上的第一硅化物层和第二硅化物层。 选择性地去除牺牲层，使得只有一部分牺牲层保留在第一硅化物层上。 在晶片之上形成层间电介质层。 层间绝缘层被平面化。 接触窗是图案。 触点被打开以显示第一硅化物层和第二硅化物层作为触点，其中形成第一硅化物层的位置高于形成第二硅化物层的位置。 此外，牺牲层的厚度Y根据以下关系确定：Y = DELTA XxRSAC /（RILD-RSAC），其中DELTA X是第一硅化物层和第二硅化物层之间的高度差，以及RSAC和RILD 是分别通过相同的蚀刻物质蚀刻牺牲层和层间电介质层的蚀刻速率。 使用牺牲层防止较浅深度的触点被过蚀刻，因此较浅的窗口中的触点的电阻将不会由于过蚀刻而异常地增加。

公开(公告)号：US5847818A

公开(公告)日：1998-12-08

申请号：US895473

申请日：1997-07-16

Applicant: Benjamin Szu-Min Lin ,  Nai-Lun Chang

Inventor： Benjamin Szu-Min Lin ,  Nai-Lun Chang

IPC: G03F7/20 ,  G01M11/00

CPC classification number: G03F7/70625 ,  G03F7/70633

Abstract: A critical dimension (CD) vernier apparatus, appropriate for scanning electron microscope (SEM) measurements, formed with additional encoding patterns. A central strip pattern is disposed along a specific direction. A first plurality of strip patterns is disposed in parallel along the specific direction and at a first side adjacent to the central strip pattern. A second plurality of strip patterns is disposed in parallel along the specific direction and at a second side adjacent to the central strip pattern. A plurality of recognition patterns is selectively added to the strip patterns whereby the central strip pattern, the recognition patterns, and the strip patterns at the first side and the second side form a specific figure to serve as a critical dimension vernier pattern. In addition, a novel critical dimension vernier, which is appropriate for measuring the compliance of contact hole dimensions to process parameters at a specific resolution is provided. The CD vernier includes a plurality of contact hole patterns disposed as an array, whereby said contact hole patterns in the first and last rows of the array and the contact hole patterns in the first and last columns of said array can be selectively varied with their dimensions such that all the contact hole patterns can form a specific pattern to serve as the critical dimension vernier.

Abstract translation: 适用于扫描电子显微镜（SEM）测量的临界尺寸（CD）游标器装置用附加编码图案形成。 沿着特定方向设置中央带状图案。 第一多个带状图案沿着特定方向并且在与中心条图案相邻的第一侧平行设置。 沿着特定方向平行地设置第二多个带状图案，并且在与中心条图案相邻的第二侧。 多个识别图案被选择性地添加到条带图案，由此中心条纹图案，识别图案和第一侧和第二侧的条纹图案形成特定图形以用作临界尺寸游标图案。 此外，提供了一种新颖的临界尺度游标，其适用于测量接触孔尺寸对特定分辨率处理参数的顺应性。 CD游标器包括多个以阵列方式设置的接触孔图案，由此阵列的第一列和最后一行中的所述接触孔图案和所述阵列的第一列和最后一列中的接触孔图案可以根据其尺寸选择性地变化 使得所有接触孔图案可以形成用作临界尺寸游标的特定图案。