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公开(公告)号：US06455416B1
公开(公告)日：2002-09-24
申请号：US09706967
申请日：2000-11-06
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/31144
摘要： One aspect of the present invention relates to a method of processing a semiconductor structure, involving the steps of providing a substrate having an insulation layer thereover; forming a first antireflection coating over the insulation layer; patterning a first resist over the antireflection coating; forming a plurality of vias in the insulation layer and the first antireflection coating, the vias having a first width; filling the via with a second antireflection coating, the second antireflection coating comprising a dye and a film forming material; patterning a second resist over the structure and removing the second antireflection coating from the via; forming a trench over the plurality of vias in the insulation layer, the trench having a width that is larger than the average width of the vias; and filling the trench and vias with a conductive material. The present invention provides improved dual damascene methods for substrates by using a developer soluble ARC containing a dye to facilitate the formation of trenches directly over the previously formed vias.
摘要翻译： 本发明的一个方面涉及一种处理半导体结构的方法，包括以下步骤：提供其上具有绝缘层的基板; 在所述绝缘层上形成第一抗反射涂层; 在抗反射涂层上图案化第一抗蚀剂; 在所述绝缘层和所述第一抗反射涂层中形成多个通孔，所述通孔具有第一宽度; 用第二抗反射涂层填充通孔，第二抗反射涂层包含染料和成膜材料; 在所述结构上形成第二抗蚀剂并从所述通孔去除所述第二抗反射涂层; 在所述绝缘层中的多个通孔上形成沟槽，所述沟槽的宽度大于所述通孔的平均宽度; 并用导电材料填充沟槽和通孔。 本发明通过使用含有染料的显影剂可溶性ARC来促进直接在先前形成的通孔上形成沟槽，从而为衬底提供改进的双镶嵌方法。
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62.发明授权UV-enhanced silylation process to increase etch resistance of ultra thin resists 失效UV增强的硅烷化方法，以增加超薄抗蚀剂的耐蚀刻性公开(公告)号：US06451512B1
公开(公告)日：2002-09-17
申请号：US09565691
申请日：2000-05-01
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur , Bryan K. Choo
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： G03F700
CPC分类号： G03F7/265 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： In one embodiment, the present invention relates to a method of processing an ultrathin resist, involving the steps of depositing the ultra-thin photoresist over a semiconductor substrate, the ultra-thin resist having a thickness less than about 3,000 Å; irradiating the ultra-thin resist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin resist; and contacting the ultra-thin resist with a silicon containing compound in an environment of at least one of ultraviolet light and ozone, wherein contact of the ultra-thin resist with the silicon containing compound is conducted between irradiating and developing the ultra-thin resist or after developing the ultra-thin resist.
摘要翻译： 在一个实施方案中，本发明涉及一种处理超薄抗蚀剂的方法，包括以下步骤：在半导体衬底上沉积超薄光致抗蚀剂，超薄抗蚀剂的厚度小于约; 用波长约250nm或更小的电磁辐射照射超薄抗蚀剂; 开发超薄抗蚀剂; 以及在紫外光和臭氧中的至少一种的环境下使超薄抗蚀剂与含硅化合物接触，其中超薄抗蚀剂与含硅化合物的接触在照射和显影超薄抗蚀剂之间进行，或 在开发超薄抗蚀剂后。
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公开(公告)号：US06248175B1
公开(公告)日：2001-06-19
申请号：US09430001
申请日：1999-10-29
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
IPC分类号： B05C1100
CPC分类号： H01L21/6715 , G03F7/3021
摘要： A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position. A method of adjusting the offset position and/or volume of developer material applied at the first and second position is also provided. The method utilizes developed photoresist material layer thickness data provided by a measurement system to adjust the offset position and/or volume of the developer.
摘要翻译： 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括适于沿着具有大致等于光致抗蚀剂材料层的直径的直线路径的光致抗蚀剂材料层上施加预定体积的显影剂材料的喷嘴。 移动系统将喷嘴移动到偏离光致抗蚀剂材料层的中心区域的第一位置，以在旋转涂覆显影剂材料的同时将第一预定体积的显影剂材料施加到光致抗蚀剂材料层。 移动系统还将喷嘴移动到偏离中心区域的第二位置，以在显影剂被旋涂时施加第二预定体积的显影剂材料到光致抗蚀剂材料层。 第一位置相对于第二位置位于中心区域的相反侧。 还提供了一种调节在第一和第二位置施加的显影剂材料的偏移位置和/或体积的方法。 该方法利用由测量系统提供的显影的光致抗蚀剂材料层厚度数据来调节显影剂的偏移位置和/或体积。
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公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译： 公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。 杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。 已知的光栅结构被构建在衬底上。 实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。
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公开(公告)号：US07153364B1
公开(公告)日：2006-12-26
申请号：US10000208
申请日：2001-10-23
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译： 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。
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公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。
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公开(公告)号：US07052575B1
公开(公告)日：2006-05-30
申请号：US09845454
申请日：2001-04-30
IPC分类号： C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67063 , H01L22/34
摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
摘要翻译： 提供了一种用于调节蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。
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68.发明授权公开(公告)号：US06931618B1
公开(公告)日：2005-08-16
申请号：US10050472
申请日：2002-01-16
摘要： A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabricating components. The control system bases its control of the fabricating components, at least in part, on feed forward control information generated by a processor that analyzes scatterometry based reticle fabrication data gathered from measurement components. The scatterometry data is compared to data stored in a signature data store that facilitates analyzing gathered scatterometry signatures to produce feed forward control information that can be employed to manipulate subsequent reticle fabrication processes and/or apparatus.
摘要翻译： 提供了一种用于选择性地生成和馈送标线制造数据的系统。 该系统包括用于制造掩模版的部件和可操作地连接到制造部件的控制系统，其中控制系统可以控制制造部件的操作。 控制系统至少部分地基于由分析从测量部件收集的基于散射仪的掩模版制造数据的处理器生成的前馈控制信息的制造部件的控制。 将散射测量数据与存储在签名数据存储器中的数据进行比较，其有助于分析所收集的散射光标签以产生可用于操纵随后的标线制造工艺和/或设备的前馈控制信息。
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公开(公告)号：US06912438B2
公开(公告)日：2005-06-28
申请号：US10277016
申请日：2002-10-21
CPC分类号： H01L22/20 , G01N21/4738 , H01L2924/0002 , H01L2924/00
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
摘要翻译： 公开了用于监测和控制半导体制造工艺的系统和方法。 根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。 可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。 另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。 在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。
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公开(公告)号：US06878560B1
公开(公告)日：2005-04-12
申请号：US10302091
申请日：2002-11-22
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G05B2219/31457 , G05B2219/32191 , G05B2219/45031 , H01L2924/0002 , H01L2924/00
摘要： A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
摘要翻译： 由多个工厂组成的系统，其可操作地耦合并且共享来自公共框架的数据以用于生产。 该晶圆厂可以通过互联网，蜂窝，光学，固定电话，微波和卫星通信装置等耦合。 可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。 制造厂发送和接收与生产信息相关的相关数据，例如公差，关键尺寸，几何形状等。 相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。 执行的计算可以包括诸如贝叶斯推理等的计算。 该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。
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