公开(公告)号：US20080131980A1

公开(公告)日：2008-06-05

申请号：US11566887

申请日：2006-12-05

申请人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

发明人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/20 ,  H01L22/14

摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.

摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。

公开(公告)号：US20060273397A1

公开(公告)日：2006-12-07

申请号：US10908926

申请日：2005-06-01

申请人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

发明人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/045

摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。 第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。 第一和第二晶体管分别形成在第一和第二区域上。 此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。 在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。

公开(公告)号：US06649429B2

公开(公告)日：2003-11-18

申请号：US10194642

申请日：2002-07-11

申请人： Edward D. Adams ,  Arne W. Ballantine ,  Richard S. Kontra ,  Alain Loiseau ,  James A. Slinkman

发明人： Edward D. Adams ,  Arne W. Ballantine ,  Richard S. Kontra ,  Alain Loiseau ,  James A. Slinkman

IPC分类号： H01L2166

CPC分类号： H01L23/544 ,  G01N2203/0016 ,  G01N2203/0025 ,  G01N2203/0286 ,  G01N2203/0617 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/34 ,  H01L29/7842 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.

公开(公告)号：US06380063B1

公开(公告)日：2002-04-30

申请号：US09516697

申请日：2000-03-01

申请人： Juan A. Chediak ,  Thomas G. Ference ,  Kurt R. Kimmel ,  Alain Loiseau ,  Randy W. Mann ,  Jed H. Rankin

发明人： Juan A. Chediak ,  Thomas G. Ference ,  Kurt R. Kimmel ,  Alain Loiseau ,  Randy W. Mann ,  Jed H. Rankin

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoining device components and prevent shorts. Sidewall spacers surrounding and extend slightly above the device gates and dielectric isolations to further prevent shorts. A layer of conductive material atop each gate and diffusion region provides for coplanar contact surfaces. A layer of silicide beneath select regions of the conductive layer enhance electrical conductivity within the device. An internal wireless interconnection to electrically connect diffusion regions of different logic devices within the structure is also provided.

摘要翻译： 具有无边界触点的半导体器件由此提供具有减小的总体尺寸的器件。 特别地，该器件包括多个浅沟槽隔离件和其上的多个绝缘隔离件，用于分离相邻的器件部件并防止短路。 侧壁间隔件围绕并延伸到器件栅极和介电隔离件的稍稍上方，以进一步防止短路。 在每个栅极和扩散区域顶部的导电材料层提供共面的接触表面。 在导电层的选择区域下方的硅化物层增强了器件内的导电性。 还提供了用于电连接结构内不同逻辑器件的扩散区域的内部无线互连。