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公开(公告)号：US07393701B2
公开(公告)日：2008-07-01
申请号：US11566887
申请日：2006-12-05
IPC分类号： H01L21/302 , H01L21/308
摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.
摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。
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公开(公告)号：US20080131980A1
公开(公告)日：2008-06-05
申请号：US11566887
申请日：2006-12-05
摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.
摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。
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公开(公告)号：US07948535B2
公开(公告)日：2011-05-24
申请号：US11948463
申请日：2007-11-30
CPC分类号： H04N5/37452 , H04N5/35527 , H04N5/3559
摘要： A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.
摘要翻译： 提供了改进的动态范围的像素传感器单元和包括体现在机器可读介质中的像素传感器单元的设计结构。 像素单元包括将电容器器件耦合到像素单元的光敏区域（例如，光电二极管）的耦合晶体管，光电二极管耦合到传输栅极和耦合晶体管的一个端子。 在操作中，当光电二极管上的电压向下拉到衬底电位时，附加电容耦合到像素单元光电二极管。 因此，当电池接近其充电容量时，所添加的电容仅连接到成像器单元。 否则，电池具有低电容和低泄漏。 在另外的实施例中，电容器的端子耦合到“脉冲”电源电压信号，其在像素传感器单元的读出操作期间使存储的电荷从电容器到光敏区域基本上完全耗尽。 在各种实施例中，增加的电容和光电二极管的位置可以相对于耦合晶体管互换。 此外，像素传感器单元的附加电容允许全局快门操作。
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公开(公告)号：US07739573B2
公开(公告)日：2010-06-15
申请号：US11621766
申请日：2007-01-10
申请人： Jonathan J. DeMent , Sang H. Dhong , Gilles Gervais , Alain Loiseau , Kirk D. Peterson , John L. Sinchak
发明人： Jonathan J. DeMent , Sang H. Dhong , Gilles Gervais , Alain Loiseau , Kirk D. Peterson , John L. Sinchak
IPC分类号： G01R31/30
CPC分类号： G01R31/3004 , G01R31/31721 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.
摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。
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公开(公告)号：US07719590B2
公开(公告)日：2010-05-18
申请号：US11687245
申请日：2007-03-16
IPC分类号： H04N5/232
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689 , H04N5/3559 , H04N5/37452
摘要： A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.
摘要翻译： 改进的动态范围的像素传感器单元包括将电容器器件耦合到像素单元的光敏区域（例如光电二极管）的耦合晶体管，光电二极管耦合到传输门和耦合晶体管的一个端子。 在操作中，当光电二极管上的电压向下拉到衬底电位时，附加电容耦合到像素单元光电二极管。 因此，当电池接近其充电容量时，所添加的电容仅连接到成像器单元。 否则，电池具有低电容和低泄漏。 在另外的实施例中，电容器的端子耦合到“脉冲”电源电压信号，其在像素传感器单元的读出操作期间使存储的电荷从电容器充分耗尽。 在各种实施例中，增加的电容和光电二极管的位置可以相对于耦合晶体管互换。 此外，像素传感器单元的附加电容允许全局快门操作。
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公开(公告)号：US07344962B2
公开(公告)日：2008-03-18
申请号：US11160365
申请日：2005-06-21
IPC分类号： H01L21/36
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。
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公开(公告)号：US07799609B2
公开(公告)日：2010-09-21
申请号：US11955436
申请日：2007-12-13
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。
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公开(公告)号：US07315066B2
公开(公告)日：2008-01-01
申请号：US10908926
申请日：2005-06-01
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.
摘要翻译： 一种半导体结构及其形成方法。 该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。 第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。 第一和第二晶体管分别形成在第一和第二区域上。 此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。 在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。
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9.发明申请UTILIZING NETWORKED 3D VOLTAGE REGULATION MODULES (VRM) TO OPTIMIZE POWER AND PERFORMANCE OF A DEVICE 有权利用网络化的3D电压调节模块（VRM）优化设备的功率和性能公开(公告)号：US20120159203A1
公开(公告)日：2012-06-21
申请号：US13399799
申请日：2012-02-17
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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10.发明申请Utilizing Networked Three Dimensional Voltage Regulation Modules (VRM) to Optimize Power and Performance of a Device 失效利用网络三维电压调节模块（VRM）来优化设备的功率和性能公开(公告)号：US20090217059A1
公开(公告)日：2009-08-27
申请号：US12037743
申请日：2008-02-26
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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