公开(公告)号：US5043942A

公开(公告)日：1991-08-27

申请号：US532627

申请日：1990-06-04

申请人： Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Hideko Odaira

发明人： Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Hideko Odaira

IPC分类号： G11C17/00 ,  G11C8/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/112

摘要： A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

摘要翻译： NAND单元型EEPROM具有基板，形成在基板上方的并行位线以及包括与相同对应位线相关联的NAND型单元单元的阵列的存储单元部分。 每个NAND型单元单元具有八个数据存储晶体管和至少一个选择晶体管的串联电路。 每个数据存储晶体管具有用于存储通过隧道注入的载流子的浮动栅极和分别连接到字线的控制栅极。 为同一位线辅助的所有NAND型单元单元共同提供控制栅极驱动电路。 传输门连接在公共驱动电路和NAND单元之间。

公开(公告)号：US4996669A

公开(公告)日：1991-02-26

申请号：US489967

申请日：1990-03-07

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

摘要翻译： 具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。 每个晶体管都有一个浮动栅极和一个控制栅极。 并行字线连接到单元晶体管的控制栅极。 在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。 将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线 其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极 存储单元晶体管。

公开(公告)号：US4875195A

公开(公告)日：1989-10-17

申请号：US46155

申请日：1987-05-05

申请人： Masaki Momodomi ,  Koji Sakui

发明人： Masaki Momodomi ,  Koji Sakui

IPC分类号： H01L27/10 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC分类号： G11C8/06

摘要： A highly-integrated semiconductor dynamic random-acess memory is disclosed wherein a reference voltage-generating circuit is connected by voltage-transmission lines to a row-address buffer and a column-address buffer. The reference voltage-generating circuit receives a power-supply voltage and generates first and second reference voltages which are different, by different values, from an ordinary reference potential level. These reference voltages are supplied to the address buffers through the voltage-transmission lines. The first and second reference voltages are adjusted to compensate for a potential deviation which occurs on the voltage-transmission lines. Therefore, even when either reference voltage fluctuates due to an increase in the coupling capacitance between the substrate of the dynamic random-access memory, on the one hand, and the voltage-transmission lines, on the other, both address buffers are prevented from malfunctioning.

摘要翻译： 公开了一种高度集成的半导体动态随机存储器，其中参考电压产生电路通过电压传输线连接到行地址缓冲器和列地址缓冲器。 参考电压发生电路接收电源电压，并产生不同于普通参考电位电平的不同值的第一和第二参考电压。 这些参考电压通过电压传输线路提供给地址缓冲器。 调整第一和第二参考电压以补偿在电压传输线上发生的电位偏差。 因此，即使由于动态随机存取存储器的基板与电压传输线之间的耦合电容的增加而导致参考电压波动，另一方面，防止两个地址缓冲器发生故障 。