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    Sense amplifier for use in an EEPROM
    1.
    发明授权
    Sense amplifier for use in an EEPROM 失效
    用于EEPROM的感应放大器

    公开(公告)号：US5740112A

    公开(公告)日：1998-04-14

    申请号：US583533

    申请日：1996-01-04

    申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

    摘要： A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.

    摘要翻译： 用于电可擦除和可编程只读存储器（EEPROM）中的信号检测用读出放大器。 读出放大器包括：第一时钟信号同步反相器，包括第一反相器和用于在第一反相器的激活和去激活状态之间切换的第一开关，第一时钟信号同步反相器具有连接到对应的一个位线的第一输入 和第一个输出。 第二时钟信号同步反相器与第一时钟信号同步反相器并联布置，并且包括第二反相器和用于在第二反相器的激活和去激活状态之间切换的第二开关，第二时钟信号同步反相器具有输入 连接到第一时钟信号同步反相器的输出端，以及连接到第一时钟信号同步反相器的输入端的输出端。 第一和第二时钟信号同步反相器中的开关被延迟激活，使得对应位线上的电位被可靠地感测并锁存在第一时钟信号同步反相器的输出端。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Non-volatile semiconductor memory device
    3.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5453955A

    公开(公告)日：1995-09-26

    申请号：US255904

    申请日：1994-06-07

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/06 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C16/26

    摘要： A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

    摘要翻译： 非挥发性半导体存储器件包括用于将位线设置在预定读取电位以执行数据读取操作的读取充电晶体管，并且在读取操作期间读取用于将未选择的位线设置为接地电位的放电晶体管。 这些晶体管由不同的控制信号控制，通过根据输入地址对每隔一个位线检测地址变化而获得，使得读出的放电晶体管保持导通，以将未选择的位线设置在地电位之前， 在数据读取操作期间。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5523980A

    公开(公告)日：1996-06-04

    申请号：US364990

    申请日：1994-12-28

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Kazunori Ohuchi ,  Tetsuo Endoh

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Kazunori Ohuchi ,  Tetsuo Endoh

    IPC分类号： G11C16/06 ,  G11C8/12 ,  G11C16/02 ,  G11C16/04 ,  G11C29/00 ,  G11C29/34 ,  H01L29/78 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C16/0483

    摘要： A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.

    摘要翻译： 具有多个位线的NAND单元型EEPROM，与位线相交的多个控制栅极线，以及通过向控制栅极线施加电位而驱动的多个存储单元，用于选择性地存储数据，向 位线和从其接收数据。 存储单元形成多个单元单元。 构成每个单元单元的存储单元通过公共选择栅极晶体管串联连接到一个位线。 分别在位线上提供多个数据锁存电路，用于存储要写入由控制栅极线选择的存储单元的数据。 此外，分别提供多个选择栅极驱动器以对应于用于驱动控制栅极线的单元单元。 行解码器解码用于驱动选择栅极驱动器和控制栅极线的行地址。 提供多个块地址锁存电路以分别对应于选择栅极驱动器，用于临时存储由行解码器从行地址导出的信号，从而同时选择至少两个选择栅极驱动器 命令写数据。

    Electrically erasable programmable read-only memory with block-erase function
    5.
    发明授权
    Electrically erasable programmable read-only memory with block-erase function 失效
    具有块擦除功能的电可擦除可编程只读存储器

    公开(公告)号：US5280454A

    公开(公告)日：1994-01-18

    申请号：US764213

    申请日：1991-09-23

    申请人： Tomoharu Tanaka ,  Yoshihisa Iwata ,  Koji Sakui ,  Masaki Momodomi

    发明人： Tomoharu Tanaka ,  Yoshihisa Iwata ,  Koji Sakui ,  Masaki Momodomi

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/16

    摘要： An EEPROM includes an array of memory cells divided into a plurality of memory blocks in a semiconductor well region in a substrate. Each block includes series arrays of FATMOS transistors each acting as one memory cell, wherein binary information may be stored in a selected cell transistor by causing carriers to tunnel between the floating gate thereof and the well region. In each block, word lines are connected to the control gates of cell transistors; control lines are to select transistors provided in the series arrays of cell transistors, with which bit lines are associated. A block-erase operation is performed such that a desired one of the memory blocks is selected for erase, while forcing the remaining memory blocks to remain non-erased. To do this, a first voltage is applied to those of the word lines of the selected block, while applying a second voltage to the remaining word lines of the non-selected blocks, the control lines of all the blocks, and the well region.

    摘要翻译： EEPROM包括在衬底中的半导体阱区中被划分成多个存储块的存储器单元的阵列。 每个块包括作为一个存储单元的FATMOS晶体管的串联阵列，其中二进制信息可以通过使载流子在其浮动栅极和阱区域之间隧穿而存储在所选择的单元晶体管中。 在每个块中，字线连接到单元晶体管的控制栅极; 控制线是选择提供在单元晶体管的串联阵列中的晶体管，与其相关联的位线。 执行块擦除操作，使得所选择的一个存储块被选择用于擦除，同时强制剩余的存储块保持不被擦除。 为此，将第一电压施加到所选块的字线的第一电压，同时对未选块的剩余字线，所有块的控制线和阱区施加第二电压。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5615163A

    公开(公告)日：1997-03-25

    申请号：US598706

    申请日：1996-02-08

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Electrically erasable programmable read-only memory with write/verify controller
    7.
    发明授权
    Electrically erasable programmable read-only memory with write/verify controller 失效
    具有写/验证控制器的电可擦除可编程只读存储器

    公开(公告)号：US5379256A

    公开(公告)日：1995-01-03

    申请号：US223307

    申请日：1994-04-05

    申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

    摘要： A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

    摘要翻译： 多个电可擦除可编程只读存储器或EEPROM与控制器LSI相关联。 每个EEPROM包括以行和列排列的浮栅隧穿存储单元晶体管阵列。 当选择提供单页数据的存储单元晶体管的子阵列进行编程时，控制器LSI通过检查所选存储单元晶体管的阈值来验证所选择的存储单元晶体管的编程之后，如下进行写入/校验操作 变化的值，并且当任何潜在的不足的单元晶体管保持在其中之间时，重复使用预定时间段的预定写入电压的重写操作，使得所得到的写入状态可能更接近可满足的参考状态。 通过将写入电压施加到不足的单元晶体管预定时间段来执行每个重写/验证操作。

    Semiconductor device with a reference voltage generator
    8.
    发明授权
    Semiconductor device with a reference voltage generator 失效
    具有参考电压发生器的半导体器件

    公开(公告)号：US4875195A

    公开(公告)日：1989-10-17

    申请号：US46155

    申请日：1987-05-05

    申请人： Masaki Momodomi ,  Koji Sakui

    发明人： Masaki Momodomi ,  Koji Sakui

    IPC分类号： H01L27/10 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    CPC分类号： G11C8/06

    摘要： A highly-integrated semiconductor dynamic random-acess memory is disclosed wherein a reference voltage-generating circuit is connected by voltage-transmission lines to a row-address buffer and a column-address buffer. The reference voltage-generating circuit receives a power-supply voltage and generates first and second reference voltages which are different, by different values, from an ordinary reference potential level. These reference voltages are supplied to the address buffers through the voltage-transmission lines. The first and second reference voltages are adjusted to compensate for a potential deviation which occurs on the voltage-transmission lines. Therefore, even when either reference voltage fluctuates due to an increase in the coupling capacitance between the substrate of the dynamic random-access memory, on the one hand, and the voltage-transmission lines, on the other, both address buffers are prevented from malfunctioning.

    摘要翻译： 公开了一种高度集成的半导体动态随机存储器，其中参考电压产生电路通过电压传输线连接到行地址缓冲器和列地址缓冲器。 参考电压发生电路接收电源电压，并产生不同于普通参考电位电平的不同值的第一和第二参考电压。 这些参考电压通过电压传输线路提供给地址缓冲器。 调整第一和第二参考电压以补偿在电压传输线上发生的电位偏差。 因此，即使由于动态随机存取存储器的基板与电压传输线之间的耦合电容的增加而导致参考电压波动，另一方面，防止两个地址缓冲器发生故障 。