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公开(公告)号：US08095821B2
公开(公告)日：2012-01-10
申请号：US12405418
申请日：2009-03-17
IPC分类号： G06F11/00
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译： 已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。 在本发明中，使用具有多个位范围的寄存器来存储错误信息。 第一个比特范围被分配给初始的错误信息。 如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。 这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。
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62.发明授权System, method and computer program product for handling shared cache lines in a multi-processor environment 失效用于在多处理器环境中处理共享缓存行的系统，方法和计算机程序产品公开(公告)号：US08032709B2
公开(公告)日：2011-10-04
申请号：US12035668
申请日：2008-02-22
CPC分类号： G06F9/3851 , G06F12/0815
摘要： A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.
摘要翻译： 提供了一种用于处理共享高速缓存行以允许处理器在多处理器环境中的前进进行的系统，方法和计算机程序产品。 为多处理器环境的处理器提供计数器和阈值，使得计数器对于跟随指令完成的每个排他交叉询问（XI）拒绝而增加，并且在独占XI确认上复位。 如果XI拒绝计数器达到预设阈值，则通过阻止指令发出和预取尝试来消除处理器的流水线，从另一个处理器创建独占XI的窗口，在此之后恢复正常指令处理。 将预设阈值配置为可编程值允许微调系统性能。
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63.发明授权公开(公告)号：US07975182B2
公开(公告)日：2011-07-05
申请号：US12036430
申请日：2008-02-25
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译： 提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。 该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。
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64.发明授权System and method for avoiding deadlocks when performing storage updates in a multi-processor environment 有权用于在多处理器环境中执行存储更新时避免死锁的系统和方法公开(公告)号：US07953932B2
公开(公告)日：2011-05-31
申请号：US12030627
申请日：2008-02-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F9/3824 , G06F9/3834 , G06F9/3867
摘要： A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion.
摘要翻译： 一种用于在多处理器环境中执行存储更新时避免死锁的系统和方法。 该系统包括具有本地高速缓存的处理器，具有临时缓冲器的存储队列，该临时缓冲器具有拒绝排他交叉询问（XI）的能力，同时询问的高速缓存行被独占地存储并被存储，以及用于执行方法的机制。 该方法包括将处理器设置为慢速模式。 接收包括具有一个或多个目标线的数据存储器的当前指令。 执行当前指令，执行包括将与数据存储相关联的结果存储到临时缓冲器中。 防止存储队列拒绝与当前指令的目标行相对应的排他的XI。 每个目标行被采集为具有独占所有权的状态，并且在指令完成之后将来自临时缓冲器的内容写入每个目标行。
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65.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING 有权系统，方法和计算机程序产品，用于增强缓存时间的推广公开(公告)号：US20090216956A1
公开(公告)日：2009-08-27
申请号：US12036476
申请日：2008-02-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译： 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。 系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。
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66.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR HANDLING SHARED CACHE LINES IN A MULTI-PROCESSOR ENVIRONMENT 失效用于在多处理器环境中处理共享缓存行的系统，方法和计算机程序产品公开(公告)号：US20090216951A1
公开(公告)日：2009-08-27
申请号：US12035668
申请日：2008-02-22
CPC分类号： G06F9/3851 , G06F12/0815
摘要： A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.
摘要翻译： 提供了一种用于处理共享高速缓存行以允许处理器在多处理器环境中的前进进行的系统，方法和计算机程序产品。 为多处理器环境的处理器提供计数器和阈值，使得计数器对于跟随指令完成的每个排他交叉询问（XI）拒绝而增加，并且在独占XI确认上复位。 如果XI拒绝计数器达到预设阈值，则通过阻止指令发出和预取尝试来消除处理器的流水线，从另一个处理器创建一个独占XI的窗口，从而恢复正常指令处理。 将预设阈值配置为可编程值允许微调系统性能。
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67.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA 失效用于采样计算机系统性能数据的方法，系统和计算机程序产品公开(公告)号：US20090210752A1
公开(公告)日：2009-08-20
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译： 提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。 该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。 该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。 响应于将仪器数据存储在采样缓冲器中，取样中断被置位。
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68.发明授权Method of implementing a translation lookaside buffer with support for a real space control 有权实现支持实际空间控制的翻译后备缓冲器的方法公开(公告)号：US06560687B1
公开(公告)日：2003-05-06
申请号：US09677345
申请日：2000-10-02
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
摘要翻译： 为了支持新的处理器控制位，在具有现有转换后备缓冲器的处理器系统中的实际空间控制（RSC）位将翻译后置缓冲器中的现有控制位，专用空间位重新定义为忽略公共段 位创建新的非重叠翻译后备缓冲区条目。
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公开(公告)号：US06233655B1
公开(公告)日：2001-05-15
申请号：US09070146
申请日：1998-04-30
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0851 , G06F12/0886
摘要： A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.
摘要翻译： 计算机处理器具有I单元（指令单元）和指令解码器，E单元（执行单元），包含统一双向交错L1高速缓存的缓冲器控制元件（BCE），并向所述双向 交错L1缓存。 处理器具有双字宽执行数据流。 在解码之前从统一高速缓存器接收指令数据的指令解码器使存储I单元逻辑在执行之前启动请求以告知缓冲器控制元件将从E单元进行存储，并且E单元逻辑 在对相应的指令数据进行解码之后发送存储请求，以指示高速缓存中要存储的DoubleWord数据的哪个地址。 在该过程中，E单元逻辑根据指令中的源地址信息和目的地址信息地址范围信息，计算出数据模式是否产生具有相同字节数据的对应多双字存储，以及当多单字 存储可能导致，它使E单元能够使用相同的地址在计算机的数据总线上请求输入双字的双字L1高速缓存交错，以便在相同周期内有效地写入两个连续寻址的DoubleWords来实现 一个四周商店在一个循环。
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70.发明授权Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法公开(公告)号：US08468306B2
公开(公告)日：2013-06-18
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。
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