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    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA
    1.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA 失效
    方法，用于生成跟踪数据的系统和计算机程序产品

    公开(公告)号：US20090216516A1

    公开(公告)日：2009-08-27

    申请号：US12036430

    申请日：2008-02-25

    申请人： Debbie A. St. Onge ,  Jane H. Bartik ,  Barry W. Krumm ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum

    发明人： Debbie A. St. Onge ,  Jane H. Bartik ,  Barry W. Krumm ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3466 ,  G06F11/3461 ,  G06F2201/885

    摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.

    摘要翻译： 提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。 该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

    Method, system and computer program product for sampling computer system performance data
    3.
    发明授权
    Method, system and computer program product for sampling computer system performance data 失效
    方法，系统和计算机程序产品，用于对计算机系统性能数据进行采样

    公开(公告)号：US07870438B2

    公开(公告)日：2011-01-11

    申请号：US12031727

    申请日：2008-02-15

    申请人： Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung Kevin Shum ,  Scott B. Swaney ,  Patrick M. West, Jr.

    发明人： Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung Kevin Shum ,  Scott B. Swaney ,  Patrick M. West, Jr.

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3636 ,  G06F11/3466 ,  G06F11/3476

    摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.

    摘要翻译： 提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。 该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。 该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。 响应于将仪器数据存储在采样缓冲器中，取样中断被置位。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA
    4.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA 失效
    用于采样计算机系统性能数据的方法，系统和计算机程序产品

    公开(公告)号：US20090210752A1

    公开(公告)日：2009-08-20

    申请号：US12031727

    申请日：2008-02-15

    申请人： Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung Kevin Shum ,  Scott B. Swaney ,  Patrick M. West, JR.

    发明人： Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung Kevin Shum ,  Scott B. Swaney ,  Patrick M. West, JR.

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3636 ,  G06F11/3466 ,  G06F11/3476

    摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.

    摘要翻译： 提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。 该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。 该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。 响应于将仪器数据存储在采样缓冲器中，取样中断被置位。

    Method and system for handling cache coherency for self-modifying code
    5.
    发明授权
    Method and system for handling cache coherency for self-modifying code 有权
    用于处理缓存一致性的自修改代码的方法和系统

    公开(公告)号：US08015362B2

    公开(公告)日：2011-09-06

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE
    7.
    发明申请
    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE 有权
    用于处理自我修改代码的高速缓存的方法和系统

    公开(公告)号：US20090210627A1

    公开(公告)日：2009-08-20

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    Store data forwarding with no memory model restrictions
    8.
    发明授权
    Store data forwarding with no memory model restrictions 有权
    存储数据转发，无内存模式限制

    公开(公告)号：US08627047B2

    公开(公告)日：2014-01-07

    申请号：US12031898

    申请日：2008-02-15

    申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0855 ,  G06F9/3826 ,  G06F9/3834

    摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.

    摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。

    MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS
    9.
    发明申请
    MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权
    微处理器和方法，用于存储存储数据的存储数据在没有存储器模型限制的系统中的背景数据

    公开(公告)号：US20090210632A1

    公开(公告)日：2009-08-20

    申请号：US12031858

    申请日：2008-02-15

    申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  David B. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  David B. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0804 ,  G06F9/30043

    摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

    摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。

    Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions
    10.
    发明授权
    Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权
    用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法

    公开(公告)号：US08468306B2

    公开(公告)日：2013-06-18

    申请号：US12031858

    申请日：2008-02-15

    申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    IPC分类号： G06F9/38

    CPC分类号： G06F12/0804 ,  G06F9/30043

    摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

    摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。