Diode structures with one or more raised terminals

    公开(公告)号:US11804543B2

    公开(公告)日:2023-10-31

    申请号:US17540339

    申请日:2021-12-02

    CPC classification number: H01L29/7391 H01L29/66356

    Abstract: Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.

    BIPOLAR TRANSISTORS
    63.
    发明申请

    公开(公告)号:US20230087058A1

    公开(公告)日:2023-03-23

    申请号:US17549013

    申请日:2021-12-13

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

    LATERAL BIPOLAR JUNCTION TRANSISTOR AND METHOD

    公开(公告)号:US20220376093A1

    公开(公告)日:2022-11-24

    申请号:US17324183

    申请日:2021-05-19

    Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

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