OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES
    61.
    发明申请
    OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES 有权
    优化的多级有限状态机与冗余直流电源

    公开(公告)号:US20140035692A1

    公开(公告)日:2014-02-06

    申请号:US13564836

    申请日:2012-08-02

    IPC分类号: H04L27/10

    CPC分类号: H03M5/145 H04L1/22

    摘要: A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel.

    摘要翻译: 公开了一种用于消除/抑制通过通信信道的长过渡运行的方法和系统。 该方法可以包括提供基于具有周期性结构的多级有限状态机(ML-FSM)的调制编码,周期性结构由预定数量的时间帧定义。 ML-FSM可以包括用于将一个时间帧中的节点连接到后续时间帧中的相同电平的节点的多个无罚币边缘,以及用于将一个时间帧中的节点连接到上一级节点的多个惩罚边 在随后的时间内。 该方法还可以包括利用基于ML-FSM的调制编码来促进在通信信道上的数据传输。

    Systems and Methods for Zone Servo Timing Gain Recovery
    64.
    发明申请
    Systems and Methods for Zone Servo Timing Gain Recovery 有权
    区域伺服定时增益恢复系统与方法

    公开(公告)号:US20130148226A1

    公开(公告)日:2013-06-13

    申请号:US13316899

    申请日:2011-12-12

    IPC分类号: G11B5/09

    CPC分类号: G11B5/59688 G11B5/59622

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is disclosed that includes Various embodiments of the present invention provide data processing systems that include an analog to digital converter circuit and a phase and gain computation circuit. The analog to digital converter circuit is operable to convert an analog input into a series of digital samples. At least a portion of the series of digitals samples represent a periodic signal from a servo data region. The phase and gain computation circuit is operable to: determine an approximate amplitude of the periodic signal based at least in part upon the digital samples representing the periodic signal from the servo data region; determine a gain based at least in part on the approximate amplitude; and determine a phase based at least in part on the approximate amplitude.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了一种数据处理系统,其包括本发明的各种实施例,其提供包括模数转换器电路和相位和增益计算电路的数据处理系统。 模数转换器电路可操作以将模拟输入转换为一系列数字采样。 一系列数字采样的至少一部分表示来自伺服数据区的周期性信号。 相位和增益计算电路可操作以:至少部分地基于表示来自伺服数据区域的周期信号的数字采样来确定周期信号的近似幅度; 至少部分地基于近似幅度确定增益; 并且至少部分地基于近似幅度来确定相位。

    Systems and Methods for Sample Averaging in Data Processing
    65.
    发明申请
    Systems and Methods for Sample Averaging in Data Processing 有权
    数据处理中样本平均的系统和方法

    公开(公告)号:US20120236429A1

    公开(公告)日:2012-09-20

    申请号:US13050765

    申请日:2011-03-17

    IPC分类号: G11B5/09 G11B5/02

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了包括读取电路和组合电路的数据处理电路。 读取电路可操作以提供用户数据集的第一实例,用户数据集的第二实例以及用户数据集的第三实例。 组合电路可操作为:将用户数据集的第一实例的至少第一段与用户数据集的第二实例的第一段组合以产生第一组合数据段; 提供第二组合数据集,其包括来自用户数据集的第二实例和用户数据集的第三实例的一个或多个第二段的组合; 并提供包括至少第一组合数据集和第二组合数据集的聚合数据集。 第二组合数据集不包括用户数据集的第一实例的第二段。

    Systems and Methods for Efficient Data Storage
    66.
    发明申请
    Systems and Methods for Efficient Data Storage 有权
    高效数据存储的系统和方法

    公开(公告)号:US20120173950A1

    公开(公告)日:2012-07-05

    申请号:US13422742

    申请日:2012-03-16

    申请人: Ming Jin Shaohua Yang

    发明人: Ming Jin Shaohua Yang

    IPC分类号: H03M13/05 G06F11/10

    摘要: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

    摘要翻译: 本发明的各种实施例提供了用于准备和访问超扇区数据集的系统和方法。 作为示例,公开了包括存储介质的数据存储系统。 存储介质包括第一伺服数据区和由用户数据区隔开的第二伺服数据区。 用户数据区域包括与公共报头数据相关联的第一码字和第二码字的一部分的至少一部分。

    Systems and Methods for Efficient Data Storage
    67.
    发明申请
    Systems and Methods for Efficient Data Storage 有权
    高效数据存储的系统和方法

    公开(公告)号:US20110246856A1

    公开(公告)日:2011-10-06

    申请号:US12750654

    申请日:2010-03-30

    申请人: Ming Jin Shaohua Yang

    发明人: Ming Jin Shaohua Yang

    IPC分类号: H03M13/05 G06F11/10

    摘要: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

    摘要翻译: 本发明的各种实施例提供了用于准备和访问超扇区数据集的系统和方法。 作为示例,公开了包括存储介质的数据存储系统。 存储介质包括第一伺服数据区和由用户数据区隔开的第二伺服数据区。 用户数据区域包括与公共报头数据相关联的第一码字和第二码字的一部分的至少一部分。

    Systems and methods for conditional positive feedback data decoding
    68.
    发明授权
    Systems and methods for conditional positive feedback data decoding 有权
    条件正反馈数据解码的系统和方法

    公开(公告)号:US09019647B2

    公开(公告)日:2015-04-28

    申请号:US13596947

    申请日:2012-08-28

    摘要: The present inventions are related to systems and methods for information data processing included selective decoder message determination. In one example, a data processing system is disclosed that includes a data decoder circuit operable to apply a conditional data decoding algorithm to a data set to yield a decoded output. The conditional decoding algorithm is operable to calculate node messages using an approach selected from a group consisting of: a first message determination mechanism, and a second message determination mechanism; where one of the first message determination mechanism and the second message determination mechanism is selected based upon a condition that includes a global iteration count applied to the data set.

    摘要翻译: 本发明涉及包括选择性解码器消息确定的信息数据处理的系统和方法。 在一个示例中,公开了一种数据处理系统,其包括数据解码器电路,其可操作以将条件数据解码算法应用于数据集以产生解码输出。 条件解码算法可操作以使用从由以下组成的组中选择的方法来计算节点消息:第一消息确定机制和第二消息确定机制; 其中基于包括应用于数据集的全局迭代计数的条件来选择第一消息确定机制和第二消息确定机制中的一个。

    Systems and methods for idle clock insertion based power control
    69.
    发明授权
    Systems and methods for idle clock insertion based power control 有权
    基于空闲时钟插入的功率控制系统和方法

    公开(公告)号:US08972761B2

    公开(公告)日:2015-03-03

    申请号:US13364217

    申请日:2012-02-01

    IPC分类号: G06F1/32

    摘要: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.

    摘要翻译: 本发明涉及用于数据处理的系统和方法,更具体地涉及用于数据处理系统中的功率治理的系统和方法。 在一个具体情况下,公开了一种系统,其包括可操作以将数据检测算法应用于与第一时钟同步的数据输入的第一数据处理电路,以及可操作以将后续数据处理算法应用于输出的第二数据处理电路 来自与第二时钟同步的第一数据处理电路,以及空闲时间执行电路,其可操作以修改第一时钟和第二时钟中的至少一个的平均频率。