Branch prediction table storing addresses with compressed high order bits
    61.
    发明授权
    Branch prediction table storing addresses with compressed high order bits 有权
    分支预测表存储具有压缩高阶位的地址

    公开(公告)号:US07949862B2

    公开(公告)日:2011-05-24

    申请号:US12195738

    申请日:2008-08-21

    IPC分类号: G06F9/38

    摘要: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

    摘要翻译: 地址控制部分包括编码部分,用于生成通过从包括在指令地址中的预定高阶和低位比特部分压缩预定高阶比特部分而产生的高阶地址信息;以及恢复部分, 从高阶地址信息命令位部分。 分支指令预测部分包括历史存储器部分,该历史存储器部分存储与从高位比特确定的多个存储位置中的任一个存储处理的分支指令相对应的高位比特部分和低位比特部分 部分和低位比特部分对应于处理的分支指令的分支地址。

    Instruction fetch control device and method thereof with dynamic configuration of instruction buffers
    62.
    发明授权
    Instruction fetch control device and method thereof with dynamic configuration of instruction buffers 有权
    指令获取控制装置及其方法,具有指令缓冲器的动态配置

    公开(公告)号:US07783868B2

    公开(公告)日:2010-08-24

    申请号:US10368670

    申请日:2003-02-20

    申请人: Masaki Ukai

    发明人: Masaki Ukai

    IPC分类号: G06F9/00 G06F15/00

    CPC分类号: G06F9/3804

    摘要: This is an instruction fetch control device supplying instructions to an instruction execution unit. The device comprises a plurality of instruction buffers storing an instruction string to be supplied to the instruction execution unit and a designation unit designating an instruction buffer storing the instruction string to be supplied next for each of the plurality of instruction buffers.

    摘要翻译: 这是向指令执行单元提供指令的指令获取控制装置。 该装置包括多个指令缓冲器,存储要提供给指令执行单元的指令串,以及指定单元,指定存储要为多个指令缓冲器中的每一个指定的下一个指令串的指令串。

    Branch predicting apparatus and branch predicting method
    63.
    发明授权
    Branch predicting apparatus and branch predicting method 失效
    分支预测装置和分支预测方法

    公开(公告)号:US07757071B2

    公开(公告)日:2010-07-13

    申请号:US10995158

    申请日:2004-11-24

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3806 G06F9/30054

    摘要: A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the call instruction, the return address in response to the return instruction is not stored in the return address stack. If so, an output selection circuit predicts a correct return target using information stored in the return address stack.

    摘要翻译: 当分支历史检测到呼叫指令的存在时,响应于与呼叫指令相对应的返回指令的返回地址被存储在返回地址堆栈中。 当分支历史在分支保留站完成执行呼叫指令之前检测到返回指令的存在时,响应于返回指令的返回地址不存储在返回地址堆栈中。 如果是,则输出选择电路使用存储在返回地址堆栈中的信息来预测正确的返回目标。

    PROCESSOR PREDICTING BRANCH FROM COMPRESSED ADDRESS INFORMATION
    64.
    发明申请
    PROCESSOR PREDICTING BRANCH FROM COMPRESSED ADDRESS INFORMATION 有权
    处理器从压缩地址信息预测分支

    公开(公告)号:US20080313446A1

    公开(公告)日:2008-12-18

    申请号:US12195738

    申请日:2008-08-21

    IPC分类号: G06F9/30

    摘要: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

    摘要翻译: 地址控制部分包括编码部分,用于生成通过从包括在指令地址中的预定高阶和低位比特部分压缩预定高阶比特部分而产生的高阶地址信息;以及恢复部分, 从高阶地址信息命令位部分。 分支指令预测部分包括历史存储器部分,该历史存储器部分存储与从高位比特确定的多个存储位置中的任一个存储处理的分支指令相对应的高位比特部分和低位比特部分 部分和低位比特部分对应于处理的分支指令的分支地址。

    Coherency maintaining device and coherency maintaining method
    65.
    发明申请
    Coherency maintaining device and coherency maintaining method 有权
    一致性维护设备和一致性维护方法

    公开(公告)号:US20080313405A1

    公开(公告)日:2008-12-18

    申请号:US12222726

    申请日:2008-08-14

    IPC分类号: G06F12/08

    摘要: A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.

    摘要翻译: 第二级高速缓存设备将第一级高速缓存设备的数据的注册信息的一部分与二级高速缓存数据单元中的注册信息相关联地存储在第二级高速缓存标签单元中,并且存储 一级缓存标签复制单元中的一级缓存设备的数据。 一致保持处理器基于存储在第二级高速缓存标签单元和第一级高速缓存标签复制单元中的信息来维护第一级高速缓存设备和第二级高速缓存设备之间的一致性。

    Cache memory and method to maintain cache-coherence between cache memory units
    66.
    发明授权
    Cache memory and method to maintain cache-coherence between cache memory units 有权
    高速缓存存储器和方法来保持高速缓冲存储单元之间的高速缓存一致性

    公开(公告)号:US07428617B2

    公开(公告)日:2008-09-23

    申请号:US10998561

    申请日:2004-11-30

    IPC分类号: G06F12/00

    CPC分类号: G06F12/1045 G06F12/0897

    摘要: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.

    摘要翻译: 缓存存储器包括存储数据的第一级高速缓冲存储器单元; 存储与存储在第一级高速缓冲存储器单元中的数据相同的数据的二级缓存存储单元; 存储单元,其存储与所述一级高速缓冲存储器单元相关的信息的一部分; 以及相干维持单元,其基于存储在所述存储单元中的信息来维持所述第一级高速缓冲存储器单元与所述第二级高速缓冲存储器单元之间的高速缓存相干性。

    Processor transferring multiple working register windows transfers global registers only for select exception handling
    67.
    发明授权
    Processor transferring multiple working register windows transfers global registers only for select exception handling 失效
    传送多个工作寄存器窗口的处理器仅传送全局寄存器,以进行选择异常处理

    公开(公告)号:US07210027B2

    公开(公告)日:2007-04-24

    申请号:US10994401

    申请日:2004-11-23

    IPC分类号: G06F9/48

    摘要: In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master register to the work register for only the global registers if the trap requires transmitting data for the global registers, thereby providing the data processing apparatus performing data transmission to the global registers if the occurring trap requires data for the global registers.

    摘要翻译: 在使用寄存器窗口方法的数据处理装置中,在异常处理期间执行从主寄存器到工作寄存器的数据传输,检测陷阱,鉴别陷阱对于全局寄存器是否需要数据传输,以及发送数据 如果陷阱需要发送全局寄存器的数据,则从主寄存器到工作寄存器仅用于全局寄存器,从而如果发生的陷阱需要全局寄存器的数据,则提供数据处理设备向全局寄存器执行数据传输。

    Data processing device with branch prediction mechanism
    69.
    发明申请
    Data processing device with branch prediction mechanism 审中-公开
    具有分支预测机制的数据处理设备

    公开(公告)号:US20060149950A1

    公开(公告)日:2006-07-06

    申请号:US11330192

    申请日:2006-01-12

    申请人: Masaki Ukai

    发明人: Masaki Ukai

    IPC分类号: G06F9/00

    摘要: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a phantom, and if the entries are not needed, they are erased. If there is an instruction that branches control flow, a phantom entry is intentionally created and instruction pre-fetching is applied to the entry.

    摘要翻译: 使用标识体模的标志和检测指令的地址与已经预测的分支的地址之间的未对准的标志来完全检测分支历史中的条目的幻像条目,其被提供用于执行分支指令的队列和控制 幻影,如果不需要条目,它们将被删除。 如果有分支控制流的指令,则有意创建幻像条目,并对条目应用指令预取。

    Pasty heat-expandable filler composition and method of sound insulation by filling closed section of car body member
    70.
    发明申请
    Pasty heat-expandable filler composition and method of sound insulation by filling closed section of car body member 审中-公开
    通过填充汽车车身部件的封闭部分,制作出可膨胀的填料组合物和隔音方法

    公开(公告)号:US20060142403A1

    公开(公告)日:2006-06-29

    申请号:US10559477

    申请日:2004-06-02

    IPC分类号: C08J9/00

    摘要: An automatic injecting type paste form heat-blowing injection composition comprising a partially crosslinked rubber, an unvulcanized rubber, a crosslinking agent, a plasticizer, a thermoplastic resin, an epoxy resin and a latent curing agent thereof, and a blowing agent. This composition can be used in a injecting and soundproofing method comprising forming an insulation wall by heating and foaming of a injection composition in a closed section of an automobile body part having a closed section frame which is produced by press molding in a body welding step of an automobile manufacturing line, and it has a good anti-stringy property and suffers form less sagging during heating and foaming.

    摘要翻译: 一种包含部分交联橡胶,未硫化橡胶,交联剂,增塑剂,热塑性树脂,环氧树脂和潜在性固化剂的自动注射型糊状热喷射组合物和发泡剂。 该组合物可用于注射和隔音方法中,包括通过在具有封闭截面框架的汽车车身部件的封闭部分中加热和发泡注射组合物来形成绝缘壁,所述封闭部分框架通过在本体焊接步骤 汽车制造生产线,具有良好的抗拉性能,在加热和发泡过程中形成较少的下垂。