公开(公告)号：US20130057219A1

公开(公告)日：2013-03-07

申请号：US13603682

申请日：2012-09-05

申请人： Hideki SAKATA

发明人： Hideki SAKATA

IPC分类号： H02J7/14

CPC分类号： H02J7/0016 ,  B60L53/24 ,  B60L58/22 ,  B60L2240/547 ,  H02J7/0021 ,  H02J7/0031 ,  Y02T10/7005 ,  Y02T10/7055 ,  Y02T10/7061 ,  Y02T10/7072 ,  Y02T90/127 ,  Y02T90/14

摘要： A power supply apparatus comprises a drive battery unit connecting a plurality of batteries in series, a voltage detection circuit, and an equalization circuit for equalizing the batteries of the drive battery unit by discharging the batteries. The equalization circuit has discharge circuits, each of which includes a discharge switch and a discharge resistor connected in series, and also as connects the discharge circuit to the battery via voltage detection lines. The voltage detection circuit has a correction circuit for detecting a correction voltage for a voltage drop in the voltage detection line by switching the discharge switch on with the discharge circuit connected to the battery. In the power supply apparatus, the voltage detection circuit detects the voltage of the battery by correcting the detected voltage of the battery being detected using the correction voltage detected by the correction circuit with the discharge switch in an ON state.

摘要翻译： 电源装置包括串联多个电池的驱动电池单元，电压检测电路和用于通过放电来均衡驱动电池单元的电池的均衡电路。 均衡电路具有放电电路，其各自包括串联连接的放电开关和放电电阻器，并且还通过电压检测线将放电电路连接到电池。 电压检测电路具有校正电路，用于通过利用连接到电池的放电电路切换放电开关来检测电压检测线中的电压降的校正电压。 在电源装置中，电压检测电路通过使用由放电开关处于ON状态的由校正电路检测到的校正电压来校正检测到的电池的检测电压来检测电池的电压。

公开(公告)号：US07743215B2

公开(公告)日：2010-06-22

申请号：US11980386

申请日：2007-10-31

申请人： Tomoyuki Okawa ,  Hiroyuki Kojima ,  Hideki Sakata ,  Masaki Ukai

发明人： Tomoyuki Okawa ,  Hiroyuki Kojima ,  Hideki Sakata ,  Masaki Ukai

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.

摘要翻译： 高速缓冲存储器控制装置控制一级（L1）高速缓存和二级（L2）高速缓存，该缓存具有被划分成用于存储来自L1高速缓存的数据的多条子行的高速缓存行。 高速缓冲存储器控制装置包括控制标志添加单元，L1高速缓存控制单元和L2高速缓存控制单元。 控制标志添加单元向每个子线提供SP标志。 L1高速缓存控制单元获取访问虚拟地址，并且当在访问虚拟地址处没有数据时，向L2高速缓存控制单元输出L2高速缓存访​​问地址。 L2缓存控制单元基于L1索引中的虚拟页号和L2索引中的物理页号来切换SP标志。 基于SP标志，相应的一条子行被写回到L1高速缓存。

公开(公告)号：US07330961B2

公开(公告)日：2008-02-12

申请号：US11009466

申请日：2004-12-13

申请人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

发明人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1054 ,  G06F12/1063

摘要： A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

摘要翻译： 高速缓存控制方法控制具有包含关系的多级高速缓存的处理器系统中的数据共享条件。 高速缓存控制方法通过实际地址对上级高速缓存进行索引，并通过虚拟地址对较低级别的高速缓存进行索引，并且防止多个不同的虚拟地址引用的实际地址在同一高速缓存中多次登记 。 多个虚拟地址可注册在高级缓存内，以便放松数据共享条件。

公开(公告)号：US20120047387A1

公开(公告)日：2012-02-23

申请号：US13373048

申请日：2011-11-03

申请人： Hideki Sakata

发明人： Hideki Sakata

IPC分类号： G06F11/30

CPC分类号： G06F12/0891 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/603 ,  Y02D10/13

摘要： A cache control device includes, in a secondary cache data unit, a clean area that stores only information that is the same information as that stored in a main storage. Then, the cache control device monitors information on electrical power consumption of the cache control device, determines whether the information on the electrical power consumption is equal to or greater than a predetermined threshold, monitors an activity ratio of a cache memory, and determines whether the activity ratio is equal to or less than a predetermined threshold. Subsequently, if the cache control device determines that the information on the electrical power consumption is equal to or greater than the predetermined threshold or determines that the activity ratio of the secondary cache memory is equal to or less than the predetermined threshold, the cache control device performs control such that the clean area in the secondary cache data unit is degenerated.

摘要翻译： 缓存控制装置在副缓存数据单元中包括仅存储与存储在主存储器中的信息相同的信息的清洁区域。 然后，高速缓存控制装置监视高速缓存控制装置的电力消耗信息，判断电力消耗的信息是否等于或大于预定阈值，监视高速缓存存储器的活动比， 活性比等于或小于预定阈值。 随后，如果高速缓存控制装置确定关于电力消耗的信息等于或大于预定阈值或者确定二级高速缓冲存储器的活动比等于或小于预定阈值，则高速缓存控制装置 执行控制，使得二次高速缓存数据单元中的清洁区域退化。

公开(公告)号：US08063506B2

公开(公告)日：2011-11-22

申请号：US12372944

申请日：2009-02-18

申请人： Hideki Sakata ,  Takeshi Oosawa ,  Akira Matsumoto

发明人： Hideki Sakata ,  Takeshi Oosawa ,  Akira Matsumoto

IPC分类号： H02H7/18

CPC分类号： H02H9/001 ,  B60L3/003 ,  B60L3/0046 ,  B60L3/04 ,  B60L2240/36 ,  B60L2270/20 ,  B60R16/03 ,  H02H3/05 ,  H02J7/0031

摘要： A power source apparatus of a car is provided with contactors (2) connected to an output-side of a battery (1); a pre-charge circuit (3) made up of a series connected pre-charge resistor (6) and a pre-charge relay (7), which is connected with a contactor (2) to supply auxiliary charge to a capacitor (21) connected to a car-side of the battery (1); and a control circuit (4) to control the contactors (2) and the pre-charge relay (7). The pre-charge resistor (6) is connected in parallel with a contactor (2), and the pre-charge relay (7) is connected in series with that contactor (2). The control circuit (4) switches the pre-charge relay (7) ON to pre-charge the car-side capacitor (21), and then switches the contactor (2) ON to connect the battery (1) to the car-side.

摘要翻译： 汽车的动力源装置设置有与电池（1）的输出侧连接的接触器（2）。 由串联连接的预充电电阻（6）和预充电继电器（7）构成的预充电电路（3），其与接触器（2）连接以向电容器（21）提供辅助电荷， 连接到电池（1）的车侧; 以及用于控制接触器（2）和预充电继电器（7）的控制电路（4）。 预充电电阻（6）与接触器（2）并联连接，并且预充电继电器（7）与该接触器（2）串联连接。 控制电路（4）将预充电继电器（7）接通，对车侧电容器（21）进行预充电，然后将接触器（2）接通，将电池（1）连接到车侧 。

公开(公告)号：US20080162818A1

公开(公告)日：2008-07-03

申请号：US11980386

申请日：2007-10-31

申请人： Tomoyuki Okawa ,  Hiroyuki Kojima ,  Hideki Sakata ,  Masaki Ukai

发明人： Tomoyuki Okawa ,  Hiroyuki Kojima ,  Hideki Sakata ,  Masaki Ukai

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.

摘要翻译： 高速缓冲存储器控制装置控制一级（L1）高速缓存和二级（L2）高速缓存，该缓存具有被划分成用于存储来自L1高速缓存的数据的多条子行的高速缓存行。 高速缓冲存储器控制装置包括控制标志添加单元，L1高速缓存控制单元和L2高速缓存控制单元。 控制标志添加单元向每个子线提供SP标志。 L1高速缓存控制单元获取访问虚拟地址，并且当在访问虚拟地址处没有数据时，向L2高速缓存控制单元输出L2高速缓存访​​问地址。 L2缓存控制单元基于L1索引中的虚拟页号和L2索引中的物理页号来切换SP标志。 基于SP标志，相应的一条子行被写回到L1高速缓存。

公开(公告)号：US20070245087A1

公开(公告)日：2007-10-18

申请号：US11802069

申请日：2007-05-18

申请人： Hideki Sakata

发明人： Hideki Sakata

IPC分类号： G06F12/00

CPC分类号： G06F15/8084

摘要： There is disclosed a data buffer device that selects and uses buffers to improve persistence of data and uniformity in use frequency of the buffers. The data buffer device includes: a REQ_QUEUE 11 constituted by plural buffers that store data and are given numbers; a mask bit vector 12 that has mask bit patterns to mask the plural buffers, respectively, and sets corresponding one of the mask bit patterns for a released buffer among the plural buffers; a first priority select section 13 that selects a buffer given the smallest number from buffers that are neither masked by the mask bit vector nor used among the plural buffers; a second priority select section 14 that selects a buffer given the smallest number from unused buffers among the plural buffers; and a selector 15 that selects one of the buffer selected by the first priority select section 13 and the buffer selected by the second priority select section 14.

摘要翻译： 公开了一种数据缓冲器件，其选择并使用缓冲器来改善数据的持久性和缓冲器的使用频率的均匀性。 数据缓冲装置包括：由多个缓冲器构成的REQ_QUEUE11，其存储数据并给出数字; 分别具有掩蔽多个缓冲器的掩码位模式的掩码位向量12，并且在多个缓冲器之间设置用于释放缓冲器的掩码位模式的对应一个; 优先选择部分13，其从不被掩码位向量屏蔽的缓冲器中选择最小数目的缓冲器，也不在多个缓冲器中使用; 第二优先级选择部分14，其从多个缓冲器中的未使用的缓冲器中选择给定最小数量的缓冲器; 以及选择器15，其选择由第一优先选择部分13选择的缓冲器和由第二优先级选择部分14选择的缓冲器之一。

公开(公告)号：US06374334B1

公开(公告)日：2002-04-16

申请号：US08954561

申请日：1997-10-20

申请人： Atsuhiro Suga ,  Akitoshi Ino ,  Tsutomu Tanaka ,  Hideki Sakata

发明人： Atsuhiro Suga ,  Akitoshi Ino ,  Tsutomu Tanaka ,  Hideki Sakata

IPC分类号： G06F1208

CPC分类号： G06F9/3824 ,  G06F12/0855

摘要： A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction. However, when the read instruction contends with the store instruction and a state transition signal, such as an instruction cancellation signal generated from an instruction controlling device, is detected, the cache write buffer controlling device changes the output signal to a storage request high signal that causes the storage operation to have precedence over the read operation.

摘要翻译： 数据处理装置将数据临时存储到高速缓存写入缓冲器，然后将数据存储在高速缓存存储装置中。 即使存储指令与用于访问高速缓存存储装置的读指令进行竞争，高速缓存存储装置优先执行另一操作的数据存储操作。 从高速缓存写入缓冲器控制装置发送到高速缓存控制装置的存储请求低信号允许读请求优先于存储指令，即使当存储在高速缓存写入缓冲器中的数据等待被传送到高速缓冲存储器时 设备响应商店指令。 然而，当读取指令与存储指令相抵触时，检测到诸如从指令控制装置产生的指令消除信号的状态转移信号时，高速缓存写入缓冲器控制装置将输出信号改变为存储请求高信号， 导致存储操作优先于读取操作。

公开(公告)号：US5497469A

公开(公告)日：1996-03-05

申请号：US939721

申请日：1992-09-02

申请人： Hideki Sakata ,  Tsutomu Tanaka ,  Takao Kato ,  Haruhiko Ueno ,  Akitoshi Ino ,  Yoshihiro Kusano

发明人： Hideki Sakata ,  Tsutomu Tanaka ,  Takao Kato ,  Haruhiko Ueno ,  Akitoshi Ino ,  Yoshihiro Kusano

IPC分类号： G06F12/10

CPC分类号： G06F12/1027

摘要： A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register. When the virtual address coincides with the other virtual address in the comparison circuit, the table entry converted by the update unit is written into an address of the main memory held in the third register.

摘要翻译： 具有用于存储地址转换表的主存储器的数据处理系统中的动态地址转换处理装置，以及通过参考地址转换表将虚拟地址转换为真实地址的中央处理单元。 中央处理单元包括用于保存虚拟地址的第一寄存器，用于保存对应于保存在第一寄存器中的虚拟地址的地址转换表的表项的第二寄存器，以及具有指示存储器中的页的更新位 被写入到第三寄存器中，用于保持保存在第二寄存器中的表条目的实际地址，比较电路，用于比较保存在第一寄存器中的虚拟地址与要转换为实际地址的另一虚拟地址;以及更新 用于更新保存在第二寄存器中的表条目中的更新位的单元。 当虚拟地址与比较电路中的另一个虚拟地址一致时，由更新单元转换的表项被写入保存在第三寄存器中的主存储器的地址。

公开(公告)号：US20090212627A1

公开(公告)日：2009-08-27

申请号：US12372944

申请日：2009-02-18

申请人： Hideki Sakata ,  Takeshi Oosawa ,  Akira Matsumoto

发明人： Hideki Sakata ,  Takeshi Oosawa ,  Akira Matsumoto

IPC分类号： H02H7/18 ,  H02J7/34

CPC分类号： H02H9/001 ,  B60L3/003 ,  B60L3/0046 ,  B60L3/04 ,  B60L2240/36 ,  B60L2270/20 ,  B60R16/03 ,  H02H3/05 ,  H02J7/0031

摘要： The car power source apparatus is provided with contactors 2 connected to the output-side of the battery 1; a pre-charge circuit 3 made up of a series connected pre-charge resistor 6 and a pre-charge relay 7, which is connected with a contactor 2 to supply auxiliary charge to a capacitor 21 connected to the car-side of the battery 1; and a control circuit 4 to control the contactors 2 and pre-charge relay 7.The pre-charge resistor 6 is connected in parallel with a contactor 2, and the pre-charge relay 7 is connected in series with that contactor 2. The control circuit 4 switches the pre-charge relay 7 ON to pre-charge the car-side capacitor 21, and then switches the contactor 2 ON to connect the battery 1 to the car-side.

摘要翻译： 轿厢电源装置设置有连接到电池1的输出侧的接触器2; 由串联连接的预充电电阻6和预充电继电器7构成的预充电电路3，其与接触器2连接，以向连接到电池1的轿厢侧的电容器21提供辅助电荷 ; 以及用于控制接触器2和预充电继电器7的控制电路4.预充电电阻器6与接触器2并联连接，并且预充电继电器7与该接触器2串联连接。控制器 电路4将预充电继电器7接通，对轿厢侧电容器21进行预充电，然后将接触器2接通以将电池1连接到轿厢侧。