Branch prediction apparatus of computer storing plural branch destination addresses
    1.
    发明授权
    Branch prediction apparatus of computer storing plural branch destination addresses 失效
    存储多个分支目的地址的计算机的分支预测装置

    公开(公告)号:US08578140B2

    公开(公告)日:2013-11-05

    申请号:US12196486

    申请日:2008-08-22

    申请人: Megumi Yokoi

    发明人: Megumi Yokoi

    IPC分类号: G06F9/00

    摘要: One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit.

    摘要翻译: 实施例的一个方面利用分支指令预测单元包括历史存储器来存储分支地址作为历史信息,选择单元参考用于选择存储位置的选择信息来选择存储位置,当选择信息的分支地址 分支指令作为历史信息存储。 在存储有多个分支地址的情况下,当在存储位置存储第一分支地址时,根据由更新所更新的选择信息,在存储位置存储第二分支地址 单元。

    Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded
    2.
    发明申请
    Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded 失效
    信息处理装置,替换方法以及记录有替换程序的计算机可读记录介质

    公开(公告)号:US20060095748A1

    公开(公告)日:2006-05-04

    申请号:US11062472

    申请日:2005-02-22

    申请人: Megumi Yokoi

    发明人: Megumi Yokoi

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3848 G06F9/3806

    摘要: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative memory device. The invention includes a selector for selecting one entry from all entries of a past branch history memory section if all entries of the past branch history memory section are in use when a branch history about a new branch instruction is registered into the past branch history memory section and a replacing section for registering the branch history about the new branch instruction into one entry selected by said selector, wherein the selector has a first selecting function of selecting one entry based on the branch history held by the past branch history memory section.

    摘要翻译: 信息处理装置技术领域本发明涉及使用分支历史寄存器来预测分支指令的分支目的地的信息处理装置,以通过使不必要的条目被选择为作为替换对象的条目来实现有效的替换,而不使用新的资源 全关联存储设备。 本发明包括一个选择器,用于当关于新的分支指令的分支历史记录到过去分支历史存储器部分中时,过去分支历史存储器部分的所有条目都被使用时,从过去分支历史存储器部分的所有条目中选择一个条目 以及用于将关于新的分支指令的分支历史记录到由所述选择器选择的一个条目中的替换部分,其中所述选择器具有基于由过去分支历史存储器部分保存的分支历史来选择一个条目的第一选择功能。

    Processor for controlling tread switching
    3.
    发明授权
    Processor for controlling tread switching 有权
    用于控制踏板切换的处理器

    公开(公告)号:US08108859B2

    公开(公告)日:2012-01-31

    申请号:US10967235

    申请日:2004-10-19

    IPC分类号: G06F9/46 G06F9/44 G06F13/00

    摘要: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

    摘要翻译: 本发明的多线程切换控制装置在使用多线程方法的信息处理装置中切换线程,并且包括在发生高速缓存未命中之后输出线程切换请求信号的线程切换请求单元,其中, 在取出指令时不存储要获取的指令,或者线程执行优先顺序改变请求单元输出线程执行优先顺序改变请求信号。

    Memory access method and information processing apparatus
    4.
    发明申请
    Memory access method and information processing apparatus 审中-公开
    存储器访问方法和信息处理装置

    公开(公告)号:US20110185128A1

    公开(公告)日:2011-07-28

    申请号:US13064568

    申请日:2011-03-31

    IPC分类号: G06F12/08

    摘要: To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs during a memory access to a secondary memory of one node, the one node judges whether a destination of the memory access is a main or the secondary memory thereof. If the memory access is destination is the main or secondary memory of the one node, the directory is indexed and retrieved to judge whether a directory hit occurs, and if no directory hit occurs, a memory access is performed by the one node based on the memory access.

    摘要翻译: 为了在其中节点被耦合的信息处理设备中保持数据一致性,将指示节点的数据取出到另一个节点的辅助存储器的取出信息存储在每个节点的目录中。 当在对一个节点的辅助存储器的存储器访问期间发生高速缓存未命中时,一个节点判断存储器访问的目的地是主存储器还是其二次存储器。 如果存储器访问是目的地是一个节点的主存储器或辅助存储器,则对目录进行索引和检索,以判断是否发生目录命中,并且如果没有发生目录命中,则基于一个节点执行存储器访问 内存访问。

    Branch predicting apparatus and branch predicting method
    5.
    再颁专利
    Branch predicting apparatus and branch predicting method 有权
    分支预测装置和分支预测方法

    公开(公告)号:USRE42466E1

    公开(公告)日:2011-06-14

    申请号:US12656111

    申请日:2010-01-15

    申请人: Megumi Yokoi

    发明人: Megumi Yokoi

    IPC分类号: G06F9/38

    摘要: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.

    摘要翻译: 分支历史存储分支指令的执行历史信息,并且预测分支指令和相应分支目的地的存在。 当完成子程序的调用指令的执行时,第一返回地址堆栈存储相应返回指令的返回目的地的地址信息。 当存在子程序的调用指令的存在时,第二返回地址堆栈存储对应返回指令的返回目的地的地址信息。 输出选择单元,当预测到返回指令的存在时,如果地址信息被存储在第二返回地址堆栈中,则选择作为具有最高优先级的分支预测结果的地址信息,并输出所选择的地址信息。

    Method and apparatus for prediction handling multiple branches simultaneously
    6.
    发明授权
    Method and apparatus for prediction handling multiple branches simultaneously 失效
    用于同时预测多个分支的方法和装置

    公开(公告)号:US07472263B2

    公开(公告)日:2008-12-30

    申请号:US10841433

    申请日:2004-05-10

    申请人: Megumi Yokoi

    发明人: Megumi Yokoi

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3848

    摘要: A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information received and a branch history of the respective branch instructions, to obtain branch prediction results.

    摘要翻译: 分支预测装置包括:分支信息接收单元,同时接收用于同时完成的多个分支指令中的每一个的分支信息;以及并行分支预测单元,对于同时完成的分支指令,并行执行分支预测,基于 接收到的分支信息和各个分支指令的分支历史,以获得分支预测结果。

    Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded
    7.
    发明申请
    Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded 审中-公开
    信息处理装置,替换方法以及记录有替换程序的计算机可读记录介质

    公开(公告)号:US20070162728A1

    公开(公告)日:2007-07-12

    申请号:US11703225

    申请日:2007-02-07

    申请人: Megumi Yokoi

    发明人: Megumi Yokoi

    IPC分类号: G06F15/00 G06F13/00

    CPC分类号: G06F9/3848 G06F9/3806

    摘要: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative memory device. The invention includes a selector for selecting one entry from all entries of a past branch history memory section if all entries of the past branch history memory section are in use when a branch history about a new branch instruction is registered into the past branch history memory section and a replacing section for registering the branch history about the new branch instruction into one entry selected by said selector, wherein the selector has a first selecting function of selecting one entry based on the branch history held by the past branch history memory section.

    摘要翻译: 信息处理装置技术领域本发明涉及使用分支历史寄存器来预测分支指令的分支目的地的信息处理装置,以通过使不必要的条目被选择为作为替换对象的条目来实现有效的替换,而不使用新的资源 全关联存储设备。 本发明包括一个选择器,用于当关于新的分支指令的分支历史记录到过去分支历史存储器部分中时,过去分支历史存储器部分的所有条目都被使用时,从过去分支历史存储器部分的所有条目中选择一个条目 以及用于将关于新的分支指令的分支历史记录到由所述选择器选择的一个条目中的替换部分,其中所述选择器具有基于由过去分支历史存储器部分保存的分支历史来选择一个条目的第一选择功能。

    Storage device and cache memory device in set associative system
    8.
    发明授权
    Storage device and cache memory device in set associative system 失效
    存储设备和缓存存储设备在集合关联系统中

    公开(公告)号:US07007136B2

    公开(公告)日:2006-02-28

    申请号:US10341456

    申请日:2003-01-14

    IPC分类号: G06F12/12

    摘要: A storage device in a set associative system includes N-pieces (N is an integer of 2 or larger) of ways each having a plurality of entries containing at least replace flags and predetermined data, an acquisition unit acquiring the replace flags contained in the entries specified by the same address from the N-pieces of ways, and a selection unit selecting a replace target way on the basis of the replace flags acquired by the acquisition unit.

    摘要翻译: 集合关联系统中的存储装置包括各自具有包含至少替换标志和预定数据的多个条目的方式的N个(N是2或更大的整数),获取单元获取包含在条目中的替换标志 由N个方式由相同的地址指定,以及选择单元,基于由获取单元获取的替换标志来选择替换目标方式。

    Branch prediction table storing addresses with compressed high order bits
    9.
    发明授权
    Branch prediction table storing addresses with compressed high order bits 有权
    分支预测表存储具有压缩高阶位的地址

    公开(公告)号:US07949862B2

    公开(公告)日:2011-05-24

    申请号:US12195738

    申请日:2008-08-21

    IPC分类号: G06F9/38

    摘要: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

    摘要翻译: 地址控制部分包括编码部分,用于生成通过从包括在指令地址中的预定高阶和低位比特部分压缩预定高阶比特部分而产生的高阶地址信息;以及恢复部分, 从高阶地址信息命令位部分。 分支指令预测部分包括历史存储器部分,该历史存储器部分存储与从高位比特确定的多个存储位置中的任一个存储处理的分支指令相对应的高位比特部分和低位比特部分 部分和低位比特部分对应于处理的分支指令的分支地址。

    Branch predicting apparatus and branch predicting method
    10.
    发明授权
    Branch predicting apparatus and branch predicting method 失效
    分支预测装置和分支预测方法

    公开(公告)号:US07757071B2

    公开(公告)日:2010-07-13

    申请号:US10995158

    申请日:2004-11-24

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3806 G06F9/30054

    摘要: A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the call instruction, the return address in response to the return instruction is not stored in the return address stack. If so, an output selection circuit predicts a correct return target using information stored in the return address stack.

    摘要翻译: 当分支历史检测到呼叫指令的存在时,响应于与呼叫指令相对应的返回指令的返回地址被存储在返回地址堆栈中。 当分支历史在分支保留站完成执行呼叫指令之前检测到返回指令的存在时,响应于返回指令的返回地址不存储在返回地址堆栈中。 如果是,则输出选择电路使用存储在返回地址堆栈中的信息来预测正确的返回目标。