摘要:
A pyridine derivative or a salt thereof expressed by the following formula 1: ##STR1## wherein W represents a group expressed by the following formula 2 or formula 3; ##STR2## wherein R.sub.1 represents an alkenyloxy group; n represents 1 or 2;Ra represents a lower alkyl group; andRb represents a halogen atom; and whereineach of R.sub.2 and R.sub.3 represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, or halogenated alkyl group;Y represents a group expressed by --S--, --NH-- or --CONH--;m represents an integer of 0 to 2; andp represents 0 or 1.The pyridine derivative has an anti-ulcer effect or an antibacterial activity against Helicobacter pyroli to be available for prevention or cure of ulcers.
摘要:
A thiadiazoleamide derivative or a salt thereof expressed by the following Formula 1: ##STR1## wherein each of R.sub.1 and R.sub.2 represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, a lower alkylamino group or an alkenyloxy group; wherein when either R.sub.1 or R.sub.2 is a hydrogen atom, the other is not a hydrogen atom; R.sub.3 represents a lower alkyl group, an aryl group, a pyridyl group or --N(R.sub.4)R.sub.5, wherein R.sub.4 and R.sub.5 represent lower alkyl groups or together represent a saturated heterocyclic ring having 4-8 members; wherein when R.sub.1 or R.sub.2 is a lower alkoxy group, R.sub.3 is --N(R.sub.4)R.sub.5 or a pyridyl group; and n represents an integer of 1-3. The derivatives have anti-ulcer effect to be available for preventing or curing ulcers in mammals.
摘要:
A main body case for storing a keyboard and an upper case for storing an integrated display/input device are coupled by first and second hinge units, disposed through a groove in the main body case, to be arbitrarily pivotal from a state wherein the keyboard faces the integrated display/input device to a state wherein the back surfaces of the keyboard and the integrated display/input device face each other.
摘要:
According to a binary data expansion processing apparatus of this invention, unicolor image data is generated in a generation section in accordance with data associated with a run length and a color instruction for designating the color of image data to be generated. Unicolor image data exceeding the generated set is combined following the already-generated image data portion in accordance with a point a0, thus generating image data for a byte block of interest. At the same time, a color change point on a reference line corresponding to the byte block of interest is detected by a b1 detector. It is checked from the detected color change point if the combined image data exceeds a byte length. If the combined image data exceeds the byte length, the combined image data for one byte of the combined image data is output to an external device.
摘要:
In a picture data record/playback system, picture data and code data is recorded onto two fields of a record, which fields constitute a single picture in an optical disk unit. When the picture data is subjected to a cyclic redundancy check and an error is detected, the first error correction, for which the bit error rate of error correction is not too high, is applied to the picture data. The code data is doubly recorded onto the optical disk unit. Both items of recorded data are compared to each other. When such items are not coincident with each other, the CRC check is applied to both items of data which are doubly recorded. The valid code data is then selected. Further, when an error is detected, a CPU executes a second error correction, under program control, of which the bit error rate for error correction is not too low.
摘要:
An information processing system using a virtual addressing for paging, including a main memory, a memory controller, a central processing unit for processing information and accessing the memory controller with a virtual address, an input/output controller for interfacing input/output devices with the memory controller and the central processing unit, a common bus for interconnecting the memory controller, the central processing unit and the input/output controller with each other. The memory controller includes a translator for translating the virtual address into a real address, whereby the virtual address is available for addressing the main memory after being translated into the real address.
摘要:
A data processing system including a central processing unit (CPU) having an operating system to process information, and a main memory coupled to the CPU to store information, wherein the CPU accesses the main memory by means of an actual address after translating an associative address into the actual address by means of the operating system. To that end, the CPU includes a dynamic address translator having a page table addressed by the associative address and outputting a portion of the actual address when being addressed by the associative address. A remaining portion of the actual address is derived from the associative address itself.
摘要:
Disclosed is an information processor provided with a main memory device capable of simultaneously reading or writing 2N bit data. 2N bit data read out from the main memory device is applied to a selector through a memory bus of 2N-bit construction. The selector devides the data comprising 2N bits in two N-bit units and then outputs that data into a scratch pad memory device constituted by N bits X M addresses. The data written in the scratch pad memory device in N bit units is processed by a central processing unit of N-bit architecture. For accessing the operand, the information processor accesses the main memory in N-bit units.
摘要:
A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store. The system includes an input circuit for simultaneously supplying to the first and second control processors a micro-instruction which the control store reads out upon receipt of said micro-address from the micro-address comparator, and a CPU-to-cache interface comparator including a second comparator circuit for comparing memory-addresses given from the first and second control processors, and then combines these memory-addresses to form one memory address and supplies the memory-address to the cache memory. The first and second control processors are simultaneously supplied with an operand which the cache memory reads out upon receipt of the memory-address from the CPU-to-cache interface comparator. The system is further provided with a fault processing circuit for supplying a clock stop signal to the first and second control processors when at least one of the first and second comparator circuits produces a non-coincidence signal, whereby the first and second control processors execute the microinstructions from the control store to carry out arithmetic operations, using the operand when necessary and stops executing the microinstructions upon receipt of the clock stop signal from the fault processing circuit.
摘要:
A glass fiber-reinforced polyamide resin molding material, comprising a polyamide resin obtained by the condensation reaction of xylylene diamine with at least one member selected from straight-chain aliphatic .alpha.,.omega.-dicarboxylic acids having 6 to 12 carbon atoms and incorporated therein, glass fiber in an amount of 5 to 50% by weight based on the total weight of the polyamide resin and the glass fiber, and a shaped article obtained by molding aforesaid molding material.