Thiadiazoleamide derivative and anti-ulcer drug
    62.
    发明授权
    Thiadiazoleamide derivative and anti-ulcer drug 有权
    噻二唑衍生物和抗溃疡药

    公开(公告)号:US5912258A

    公开(公告)日:1999-06-15

    申请号:US157376

    申请日:1998-09-21

    CPC分类号: C07D285/135 C07D417/12

    摘要: A thiadiazoleamide derivative or a salt thereof expressed by the following Formula 1: ##STR1## wherein each of R.sub.1 and R.sub.2 represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, a lower alkylamino group or an alkenyloxy group; wherein when either R.sub.1 or R.sub.2 is a hydrogen atom, the other is not a hydrogen atom; R.sub.3 represents a lower alkyl group, an aryl group, a pyridyl group or --N(R.sub.4)R.sub.5, wherein R.sub.4 and R.sub.5 represent lower alkyl groups or together represent a saturated heterocyclic ring having 4-8 members; wherein when R.sub.1 or R.sub.2 is a lower alkoxy group, R.sub.3 is --N(R.sub.4)R.sub.5 or a pyridyl group; and n represents an integer of 1-3. The derivatives have anti-ulcer effect to be available for preventing or curing ulcers in mammals.

    摘要翻译: 由下式1表示的噻二唑衍生物或其盐:其中R 1和R 2各自表示氢原子,低级烷基,低级烷氧基,低级烷基氨基或烯氧基; 其中当R 1或R 2是氢原子时,另一个不是氢原子; R3表示低级烷基,芳基,吡啶基或-N(R4)R5,其中R4和R5代表低级烷基或一起代表具有4-8个成员的饱和杂环; 其中当R1或R2为低级烷氧基时,R3为-N(R4)R5或吡啶基; n表示1-3的整数。 该衍生物具有抗溃疡作用,可用于预防或治疗哺乳动物的溃疡。

    Binary data compression and expansion processing apparatus
    64.
    发明授权
    Binary data compression and expansion processing apparatus 失效
    二进制数据压缩和扩展处理装置

    公开(公告)号:US4760459A

    公开(公告)日:1988-07-26

    申请号:US18281

    申请日:1987-02-24

    IPC分类号: G06T9/00 H04N1/417 H04N1/413

    CPC分类号: H04N1/4175 G06T9/005

    摘要: According to a binary data expansion processing apparatus of this invention, unicolor image data is generated in a generation section in accordance with data associated with a run length and a color instruction for designating the color of image data to be generated. Unicolor image data exceeding the generated set is combined following the already-generated image data portion in accordance with a point a0, thus generating image data for a byte block of interest. At the same time, a color change point on a reference line corresponding to the byte block of interest is detected by a b1 detector. It is checked from the detected color change point if the combined image data exceeds a byte length. If the combined image data exceeds the byte length, the combined image data for one byte of the combined image data is output to an external device.

    摘要翻译: 根据本发明的二进制数据扩展处理装置,根据与游程长度相关联的数据和用于指定要生成的图像数据的颜色的颜色指示,在生成部分中生成单色图像数据。 超过生成集合的单色图像数据根据点a0在已经生成的图像数据部分之后被组合,从而生成用于感兴趣的字节块的图像数据。 同时,由b1检测器检测与感兴趣的字节块相对应的参考线上的颜色变化点。 如果组合的图像数据超过字节长度,则从检测到的颜色变化点检查。 如果组合图像数据超过字节长度,则将组合图像数据的一个字节的组合图像数据输出到外部设备。

    Data processing system with error correction
    65.
    发明授权
    Data processing system with error correction 失效
    具有纠错的数据处理系统

    公开(公告)号:US4604748A

    公开(公告)日:1986-08-05

    申请号:US567912

    申请日:1984-01-03

    申请人: Fumitaka Sato

    发明人: Fumitaka Sato

    CPC分类号: G06F11/1076 G06F11/1008

    摘要: In a picture data record/playback system, picture data and code data is recorded onto two fields of a record, which fields constitute a single picture in an optical disk unit. When the picture data is subjected to a cyclic redundancy check and an error is detected, the first error correction, for which the bit error rate of error correction is not too high, is applied to the picture data. The code data is doubly recorded onto the optical disk unit. Both items of recorded data are compared to each other. When such items are not coincident with each other, the CRC check is applied to both items of data which are doubly recorded. The valid code data is then selected. Further, when an error is detected, a CPU executes a second error correction, under program control, of which the bit error rate for error correction is not too low.

    摘要翻译: 在图像数据记录/重放系统中,将图像数据和代码数据记录在记录的两个场上,这些场构成光盘单元中的单个图像。 当对图像数据进行循环冗余校验并检测出错误时,对图像数据应用误差校正的误码率不太高的第一纠错。 代码数据被双重记录在光盘单元上。 记录数据的两个项目被相互比较。 当这些项目彼此不一致时,CRC校验被应用于被双重记录的两个数据项。 然后选择有效的代码数据。 此外,当检测到错误时,CPU在程序控制下执行错误校正的误码率不太低的第二纠错。

    Information processing system
    66.
    发明授权
    Information processing system 失效
    信息处理系统

    公开(公告)号:US4513369A

    公开(公告)日:1985-04-23

    申请号:US349698

    申请日:1982-02-17

    申请人: Fumitaka Sato

    发明人: Fumitaka Sato

    IPC分类号: G06F12/12 G06F12/10 G06F9/00

    CPC分类号: G06F12/1027 G06F12/1081

    摘要: An information processing system using a virtual addressing for paging, including a main memory, a memory controller, a central processing unit for processing information and accessing the memory controller with a virtual address, an input/output controller for interfacing input/output devices with the memory controller and the central processing unit, a common bus for interconnecting the memory controller, the central processing unit and the input/output controller with each other. The memory controller includes a translator for translating the virtual address into a real address, whereby the virtual address is available for addressing the main memory after being translated into the real address.

    摘要翻译: 一种使用虚拟寻址寻呼的信息处理系统,包括主存储器,存储器控制器,用于处理信息的中央处理单元和用虚拟地址访问存储器控制器;输入/输出控制器,用于将输入/输出设备与 存储器控制器和中央处理单元,用于将存储器控制器,中央处理单元和输入/输出控制器互相互连的公共总线。 存储器控制器包括用于将虚拟地址转换为实际地址的翻译器,由此虚拟地址可用于在翻译成真实地址之后寻址主存储器。

    Data processing system with improved address translation facility
    67.
    发明授权
    Data processing system with improved address translation facility 失效
    数据处理系统,具有改进的地址转换设备

    公开(公告)号:US4491911A

    公开(公告)日:1985-01-01

    申请号:US351859

    申请日:1982-02-24

    申请人: Fumitaka Sato

    发明人: Fumitaka Sato

    IPC分类号: G06F12/10 G06F13/00 G06F9/30

    CPC分类号: G06F12/10 G06F12/1027

    摘要: A data processing system including a central processing unit (CPU) having an operating system to process information, and a main memory coupled to the CPU to store information, wherein the CPU accesses the main memory by means of an actual address after translating an associative address into the actual address by means of the operating system. To that end, the CPU includes a dynamic address translator having a page table addressed by the associative address and outputting a portion of the actual address when being addressed by the associative address. A remaining portion of the actual address is derived from the associative address itself.

    摘要翻译: 一种数据处理系统,包括具有用于处理信息的操作系统的中央处理单元(CPU),以及耦合到CPU以存储信息的主存储器,其中CPU在转换关联地址之后借助于实际地址访问主存储器 通过操作系统进入实际地址。 为此,CPU包括具有由关联地址寻址的页表的动态地址转换器,并且在通过关联地址寻址时输出实际地址的一部分。 实际地址的剩余部分从关联地址本身导出。

    Information processor
    68.
    发明授权
    Information processor 失效
    信息处理器

    公开(公告)号:US4489395A

    公开(公告)日:1984-12-18

    申请号:US375702

    申请日:1982-05-06

    申请人: Fumitaka Sato

    发明人: Fumitaka Sato

    IPC分类号: G06F13/40 G06F13/00

    CPC分类号: G06F13/4018

    摘要: Disclosed is an information processor provided with a main memory device capable of simultaneously reading or writing 2N bit data. 2N bit data read out from the main memory device is applied to a selector through a memory bus of 2N-bit construction. The selector devides the data comprising 2N bits in two N-bit units and then outputs that data into a scratch pad memory device constituted by N bits X M addresses. The data written in the scratch pad memory device in N bit units is processed by a central processing unit of N-bit architecture. For accessing the operand, the information processor accesses the main memory in N-bit units.

    摘要翻译: 公开了一种具有能够同时读取或写入2N位数据的主存储器的信息处理器。 从主存储器件读出的2N位数据通过2N位结构的存储器总线施加到选择器。 选择器将包括2N位的数据分成两个N位单元,然后将该数据输出到由N位X M地址构成的暂存存储器件中。 以N位单位写入暂存器存储器件的数据由N位结构的中央处理单元处理。 对于访问操作数,信息处理器以N位为单位访问主存储器。

    Data processing system having redundant control processors for fault
detection
    69.
    发明授权
    Data processing system having redundant control processors for fault detection 失效
    具有用于故障检测的冗余控制处理器的数据处理系统

    公开(公告)号:US4456952A

    公开(公告)日:1984-06-26

    申请号:US204553

    申请日:1980-11-06

    IPC分类号: G06F11/14 G06F11/16 G06F15/16

    摘要: A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store. The system includes an input circuit for simultaneously supplying to the first and second control processors a micro-instruction which the control store reads out upon receipt of said micro-address from the micro-address comparator, and a CPU-to-cache interface comparator including a second comparator circuit for comparing memory-addresses given from the first and second control processors, and then combines these memory-addresses to form one memory address and supplies the memory-address to the cache memory. The first and second control processors are simultaneously supplied with an operand which the cache memory reads out upon receipt of the memory-address from the CPU-to-cache interface comparator. The system is further provided with a fault processing circuit for supplying a clock stop signal to the first and second control processors when at least one of the first and second comparator circuits produces a non-coincidence signal, whereby the first and second control processors execute the microinstructions from the control store to carry out arithmetic operations, using the operand when necessary and stops executing the microinstructions upon receipt of the clock stop signal from the fault processing circuit.

    摘要翻译: 一种数据处理系统,包括用于存储由多个微指令构成的微程序的控制存储器,以双重方式连接的第一和第二控制处理器,用于在微程序控制下同时处理数据;以及高速缓冲存储器,用于存储数据的一部分 存储在主存储器中。 该系统比较来自第一和第二控制处理器的微地址,并组合微地址以形成一个微地址,并将微地址提供给控制存储。 该系统包括一个输入电路,用于同时向第一和第二控制处理器提供微指令,该微指令在从微地址比较器接收到所述微地址时读出,以及CPU到高速缓存接口比较器,包括 第二比较器电路,用于比较从第一和第二控制处理器给出的存储器地址,然后组合这些存储器地址以形成一个存储器地址,并将存储器地址提供给高速缓冲存储器。 第一和第二控制处理器同时被提供有操作数,高速缓冲存储器在从CPU到高速缓存接口比较器接收到存储器地址时读出。 该系统还设置有故障处理电路,用于当第一和第二比较器电路中的至少一个产生不一致信号时,向第一和第二控制处理器提供时钟停止信号,由此第一和第二控制处理器执行 来自控制存储器的微指令进行算术运算,在必要时使用操作数,并在从故障处理电路接收到时钟停止信号时停止执行微指令。

    Glass fiber-reinforced polyamide resin molding material
    70.
    发明授权
    Glass fiber-reinforced polyamide resin molding material 失效
    玻璃纤维增​​强聚酰胺树脂成型材料

    公开(公告)号:US3962524A

    公开(公告)日:1976-06-08

    申请号:US510860

    申请日:1974-09-30

    IPC分类号: C08L77/00 C08K7/14 B32B27/34

    摘要: A glass fiber-reinforced polyamide resin molding material, comprising a polyamide resin obtained by the condensation reaction of xylylene diamine with at least one member selected from straight-chain aliphatic .alpha.,.omega.-dicarboxylic acids having 6 to 12 carbon atoms and incorporated therein, glass fiber in an amount of 5 to 50% by weight based on the total weight of the polyamide resin and the glass fiber, and a shaped article obtained by molding aforesaid molding material.

    摘要翻译: 一种玻璃纤维增​​强聚酰胺树脂成型材料,其包含通过苯二胺与选自碳原子数6〜12的直链脂肪族α,ω-二羧酸和其中的至少一种的缩合反应得到的聚酰胺树脂, 相对于聚酰胺树脂和玻璃纤维的总重量为5〜50重量%的纤维,以及通过成型上述成型材料而成型的成型体。