公开(公告)号：US07277320B2

公开(公告)日：2007-10-02

申请号：US10550105

申请日：2004-03-23

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/14 ,  G11C7/02

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/224

摘要： A magnetic memory device and a sense amplifier circuit capable of obtaining a read signal output with a high S/N ratio and reducing power consumption and a circuit space, and a method of reading from a magnetic memory device are provided. In a sense amplifier, transistors (41A), (41B) which are differential amplifiers are commonly connected to one constant current circuit (50) through switches (46) ( . . . , 46n, 46n+1, . . . ). Corresponding bit decode lines (20) ( . . . , 20n, 20n+1, . . . ) and a read selection signal line (90) are connected to the switches (46) ( . . . , 46n, 46n+1, . . . ). A read/write signal is transferred from the read selection signal line (90), and the switches (46) operate according to a bit decode value and the read/write signal.

摘要翻译： 提供一种能够获得高S / N比的读取信号输出并降低功耗和电路空间的磁存储器件和读出放大器电路，以及从磁存储器件读取的方法。 在读出放大器中，作为差分放大器的晶体管（41A），（41B）通过开关（46）（...，46 n，46 n + 1，...）共同连接到一个恒流电路（50）。 。）。 相应的位解码线（20）（...，20 n，20 n + 1，...）和读选择信号线（90）连接到开关（46）（...，46 n，46 n + 1，...）。 读/写信号从读取选择信号线（90）传送，并且开关（46）根据位解码值和读/写信号进行操作。

公开(公告)号：US07209380B2

公开(公告)日：2007-04-24

申请号：US10547508

申请日：2004-03-12

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/224 ,  H01L27/226

摘要： The present invention provides a magnetic memory device capable of performing reading operation with lower power consumption and at high read precision and a method of reading the magnetic memory device. Sense bit lines (21A, 21B) are provided in a bit line direction for each pair of magnetoresistive devices (12A, 12B) constructing a storage cell (12) and a read current is supplied. The read currents passed through the pair of magnetoresistive devices (12A, 12B) flow to the ground via a sense word line (31). Further, by providing a constant current circuit (108B) commonly for plural sense word lines (31), the sum of a pair of read currents passing through the pair of magnetoresistive devices (12A, 12B) in one storage cell constant, and information is read from the storage cell (12) on the basis of the difference between the pair of read currents. By sharing the constant current circuit (108B), variations in the sum of the pair of read currents can be reduced, and power consumption can be also reduced.

摘要翻译： 本发明提供一种能够以较低的功耗和高读取精度执行读取操作的磁存储器件以及读取该磁性存储器件的方法。 对于构成存储单元（12）的每对磁阻器件（12A，12B），沿位线方向设置感测位线（21A，21B），并提供读取电流。 通过一对磁阻器件（12A，12B）的读取电流通过感测字线（31）流到地。 此外，通过为多个感测字线（31）共同设置恒流电路（108B），在一个存储单元中通过一对磁阻器件（12A，12B）的一对读电流的总和恒定， 并且基于一对读取电流之间的差，从存储单元（12）读取信息。 通过共享恒流电路（108B），可以减小一对读取电流之和的变化，并且还可以降低功耗。

公开(公告)号：US20060120145A1

公开(公告)日：2006-06-08

申请号：US10547508

申请日：2004-03-12

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/224 ,  H01L27/226

摘要： The present invention provides a magnetic memory device capable of performing reading operation with lower power consumption and at high read precision and a method of reading the magnetic memory device. Sense bit lines (21A, 21B) are provided in a bit line direction for each pair of magnetoresistive devices (12A, 12B) constructing a storage cell (12) and a read current is supplied. The read currents passed through the pair of magnetoresistive devices (12A, 12B) flow to the ground via a sense word line (31). Further, by providing a constant current circuit (108B) commonly for plural sense word lines (31), the sum of a pair of read currents passing through the pair of magnetoresistive devices (12A, 12B) in one storage cell constant, and information is read from the storage cell (12) on the basis of the difference between the pair of read currents. By sharing the constant current circuit (108B), variations in the sum of the pair of read currents can be reduced, and power consumption can be also reduced.

摘要翻译： 本发明提供一种能够以较低的功耗和高读取精度执行读取操作的磁存储器件以及读取该磁性存储器件的方法。 对构成存储单元（12）的每对磁阻器件（12A，12B）的位线方向设置感测位线（21A，21B），并提供读取电流。 通过一对磁阻器件（12A，12B）的读取电流通过感测字线（31）流到地。 此外，通过为多个感测字线（31）共同设置恒流电路（108B），在一个存储单元中通过一对磁阻器件（12A，12B）的一对读电流的总和恒定， 并且基于一对读取电流之间的差，从存储单元（12）读取信息。 通过共享恒流电路（108B），可以减小一对读取电流之和的变化，并且还可以降低功耗。

公开(公告)号：US5097391A

公开(公告)日：1992-03-17

申请号：US599414

申请日：1990-10-18

申请人： Takeshi Nomura ,  Masaaki Ikeda ,  Shigekazu Sumita ,  Yukie Nakano ,  Kousuke Nishiyama ,  Michio Abe

发明人： Takeshi Nomura ,  Masaaki Ikeda ,  Shigekazu Sumita ,  Yukie Nakano ,  Kousuke Nishiyama ,  Michio Abe

IPC分类号： H01G4/12 ,  H01G4/30

CPC分类号： H01G4/30 ,  H01G4/1281 ,  Y10T29/435

摘要： In a ceramic multilayer chip capacitor comprising alternately stacked internal electrodes of Ni or Ni alloy and dielectric layers, an oxide layer having a different composition from the dielectric layer is formed on the periphery of each internal electrode. The dielectric layer consists essentially of grains and a grain boundary phase, the percent area of the grain boundary phase being up to 2% of the area of a cross section of the dielectric layer. The capacitor is prepared by alternately stacking Ni or Ni alloy and a dielectric material in layer form, firing and then heat treating the stack under predetermined oxygen partial pressures. The dielectric material is a barium titanate base oxide material. The capacitor has a long effective life.

公开(公告)号：US5032838A

公开(公告)日：1991-07-16

申请号：US428287

申请日：1989-10-26

申请人： Masayoshi Murayama ,  Fumitaka Sato ,  Kensuke Adachi ,  Shigekazu Sumita

发明人： Masayoshi Murayama ,  Fumitaka Sato ,  Kensuke Adachi ,  Shigekazu Sumita

IPC分类号： H03M7/40 ,  H03M7/42

CPC分类号： H03M7/425

摘要： When a variable length code requires two cycles in decoding, portions of code bit strings serving as objects to be decoded in first and second cycles of the variable length code are caused to overlap each other. In the first cycle, a non-overlapping portion is determined as a decoded portion. A length of a code bit string actually decoded in the first cycle is determined as a length of the code bit string serving as the object to be decoded in the first cycle excluding the length of the overlapping portion so as to determine a start position of the code bit string serving as the object to be decoded in the second cycle.

摘要翻译： 当可变长度代码在解码中需要两个周期时，引起用作可变长度码的第一和第二周期中要解码的对象的码位串的部分彼此重叠。 在第一周期中，将非重叠部分确定为解码部分。 在第一周期中实际解码的码位串的长度被确定为用作除了重叠部分的长度之外的第一周期中要解码的对象的码位串的长度，以便确定 用作第二周期中要解码的对象的码位串。

公开(公告)号：US07342822B2

公开(公告)日：2008-03-11

申请号：US10540400

申请日：2004-01-15

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/00

CPC分类号： H01L27/224 ,  G11C11/1675

摘要： The number of write circuit components, variations in a write current flowing through each write line, and the power consumption for write operation can be reduced. A first constant current circuit and a second constant current circuit (a transistor (Q8) and a resistor (R4), and a transistor (Q7) and a resistor (R3)) are shared among a plurality of current direction control portions (54n−1, 54n, 54n+1, . . . ). The constant current circuits are connected to each current direction control portion (54) through a first circuit selector switch (SW1 . . . , SW1n, SW1n+1, . . . ) and a second circuit selector switch (SW2 . . . , SW2n, SW2n+1, . . . ) disposed for each current direction control portion (54). Moreover, a decode signal voltage is applied to the constant current circuits from a word decode line (16X) (bit decode line (16Y)) through the circuit selector switches (SW1) and (SW2).

摘要翻译： 可以减少写入电路组件的数量，流过每条写入线的写入电流的变化以及写入操作的功耗。 第一恒流电路和第二恒流电路（晶体管（Q 8）和电阻器（R 4）以及晶体管（Q 7）和电阻器（R 3））在多个电流方向控制 部分（54 n-1，54 n，54 n + 1，...）。 恒流电路通过第一电路选择开关（SW 1 ... SW 1 n，SW 1 n + 1 ...）和第二电路选择开关（SW）连接到每个电流方向控制部分（54） 2，...，SW 2 n，SW 2 n + 1，...，）设置在每个电流方向控制部分（54）上。 此外，通过电路选择开关（SW 1）和（SW 2），从字解码线（16×）（位解码线（16Y））向定电流电路施加解码信号电压。

公开(公告)号：US20060098478A1

公开(公告)日：2006-05-11

申请号：US10550201

申请日：2004-03-26

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16 ,  H01L27/224

摘要： The present invention provides a magnetic memory device based on a novel driving method realizing reliable writing and a method of writing the magnetic memory device. Four parallel portions are formed in a pair of loop-shaped write lines (6Xn) and (6Yn). Magnetoresistive devices (12A) and (12B) disposed in the parallel portion in an upper stage construct a memory cell (12Ev), and magnetoresistive devices (12A) and (12B) disposed in the parallel portion in a lower stage construct a memory cell (120d). When current in the direction from the drive point A to the drive point B is passed from the current drives (123n) and (133n), the directions of the currents in the write lines (6Xn) and (6Yn) are aligned in the parallel portion of the memory cell (12Ev) but are opposite to each other in the parallel portion in the memory cell (120d). In the memory cell (12Ev), induced magnetic fields enhance each other, and the magnetization directions of the magneto-sensitive layers of the magnetoresistive devices (12A) and (12B) are anti-parallel with each other. In the memory cell (120d), the induced magnetic fields cancel each other out.

摘要翻译： 本发明提供了一种基于实现可靠写入的新型驱动方法和一种写入磁存储器件的方法的磁存储器件。 在一对环形写入线（6Xn）和（6Yn）中形成四个平行部分。 设置在上级的平行部分中的设置在存储单元（12Ev）中的磁阻器件（12A）和（12B），以及设置在下级的平行部分中的磁阻器件（12A）和（12A） 构建存储单元（120d）。 当从驱动点A到驱动点B的方向的电流从电流驱动器（123 n）和（133 n）通过时，写入线（6 Xn）和（6 Yn）中的电流方向为 在存储单元（12Ev）的平行部分对齐，但是在存储单元（120d）的平行部分中彼此相对。 在存储单元（12Ev）中，感应磁场彼此增强，并且磁阻器件（12A）和（12B）的磁敏层的磁化方向彼此反平行。 在存储单元（120d）中，感应磁场相互抵消。

公开(公告)号：US4760459A

公开(公告)日：1988-07-26

申请号：US18281

申请日：1987-02-24

申请人： Fumitaka Sato ,  Shigekazu Sumita ,  Masayoshi Murayama ,  Hiromichi Tome

发明人： Fumitaka Sato ,  Shigekazu Sumita ,  Masayoshi Murayama ,  Hiromichi Tome

IPC分类号： G06T9/00 ,  H04N1/417 ,  H04N1/413

CPC分类号： H04N1/4175 ,  G06T9/005

摘要： According to a binary data expansion processing apparatus of this invention, unicolor image data is generated in a generation section in accordance with data associated with a run length and a color instruction for designating the color of image data to be generated. Unicolor image data exceeding the generated set is combined following the already-generated image data portion in accordance with a point a0, thus generating image data for a byte block of interest. At the same time, a color change point on a reference line corresponding to the byte block of interest is detected by a b1 detector. It is checked from the detected color change point if the combined image data exceeds a byte length. If the combined image data exceeds the byte length, the combined image data for one byte of the combined image data is output to an external device.

摘要翻译： 根据本发明的二进制数据扩展处理装置，根据与游程长度相关联的数据和用于指定要生成的图像数据的颜色的颜色指示，在生成部分中生成单色图像数据。 超过生成集合的单色图像数据根据点a0在已经生成的图像数据部分之后被组合，从而生成用于感兴趣的字节块的图像数据。 同时，由b1检测器检测与感兴趣的字节块相对应的参考线上的颜色变化点。 如果组合的图像数据超过字节长度，则从检测到的颜色变化点检查。 如果组合图像数据超过字节长度，则将组合图像数据的一个字节的组合图像数据输出到外部设备。

公开(公告)号：US07230843B2

公开(公告)日：2007-06-12

申请号：US10550201

申请日：2004-03-26

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11C11/14

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16 ,  H01L27/224

摘要： The present invention provides a magnetic memory device based on a novel driving method realizing reliable writing and a method of writing the magnetic memory device. Four parallel portions are formed in a pair of loop-shaped write lines (6Xn) and (6Yn). Magnetoresistive devices (12A) and (12B) disposed in the parallel portion in an upper stage construct a memory cell (12Ev), and magnetoresistive devices (12A) and (12B) disposed in the parallel portion in a lower stage construct a memory cell (12Od). When current in the direction from the drive point A to the drive point B is passed from the current drives (123n) and (133n), the directions of the currents in the write lines (6Xn) and (6Yn) are aligned in the parallel portion of the memory cell (12Ev) but are opposite to each other in the parallel portion in the memory cell (12Od). In the memory cell (12Ev), induced magnetic fields enhance each other, and the magnetization directions of the magneto-sensitive layers of the magnetoresistive devices (12A) and (12B) are anti-parallel with each other. In the memory cell (12Od), the induced magnetic fields cancel each other out.

摘要翻译： 本发明提供了一种基于实现可靠写入的新型驱动方法和一种写入磁存储器件的方法的磁存储器件。 在一对环形写入线（6Xn）和（6Yn）中形成四个平行部分。 设置在上级的平行部分中的设置在存储单元（12Ev）中的磁阻器件（12A）和（12B），以及设置在下级的平行部分中的磁阻器件（12A）和（12A） 构建一个存储单元（12 Od）。 当从驱动点A到驱动点B的方向的电流从电流驱动器（123 n）和（133 n）通过时，写入线（6 Xn）和（6 Yn）中的电流方向为 在存储单元（12Ev）的平行部分中排列，但是在存储单元（12OD）的平行部分中彼此相对。 在存储单元（12Ev）中，感应磁场彼此增强，并且磁阻器件（12A）和（12B）的磁敏层的磁化方向彼此反平行。 在存储单元（12 Od）中，感应磁场相互抵消。

公开(公告)号：US20060256461A1

公开(公告)日：2006-11-16

申请号：US10540400

申请日：2004-01-15

申请人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

发明人： Joichiro Ezaki ,  Yuji Kakinuma ,  Keiji Koga ,  Shigekazu Sumita

IPC分类号： G11B5/00

CPC分类号： H01L27/224 ,  G11C11/1675

摘要： The number of write circuit components, variations in a write current flowing through each write line, and the power consumption for write operation can be reduced. A first constant current circuit and a second constant current circuit (a transistor (Q8) and a resistor (R4), and a transistor (Q7) and a resistor (R3)) are shared among a plurality of current direction control portions (54n−1, 54n, 54n+1, . . . ). The constant current circuits are connected to each current direction control portion (54) through a first circuit selector switch (SW1 . . . , SW1n, SW1n+1, . . . ) and a second circuit selector switch (SW2 . . . , SW2n, SW2n+1, . . . ) disposed for each current direction control portion (54). Moreover, a decode signal voltage is applied to the constant current circuits from a word decode line (16X) (bit decode line (16Y)) through the circuit selector switches (SW1) and (SW2).

摘要翻译： 可以减少写入电路组件的数量，流过每条写入线的写入电流的变化以及写入操作的功耗。 第一恒流电路和第二恒流电路（晶体管（Q 8）和电阻器（R 4）以及晶体管（Q 7）和电阻器（R 3））在多个电流方向控制 部分（54 n-1，54 n，54 n + 1，...）。 恒流电路通过第一电路选择开关（SW 1 ... SW 1 n，SW 1 n + 1 ...）和第二电路选择开关（SW）连接到每个电流方向控制部分（54） 2，...，SW 2 n，SW 2 n + 1，...，）设置在每个电流方向控制部分（54）上。 此外，通过电路选择开关（SW 1）和（SW 2），从字解码线（16×）（位解码线（16Y））向定电流电路施加解码信号电压。