公开(公告)号：US20110273116A1

公开(公告)日：2011-11-10

申请号：US12929779

申请日：2011-02-15

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： H02K7/14 ,  G05F1/00 ,  H03K3/00

CPC分类号： H03K17/166 ,  H03K17/08122 ,  H03K17/0822 ,  H03K17/167 ,  H03K2217/0063 ,  H03K2217/0081

摘要： A power device includes a switching device and a control unit. The switching device has a control terminal and an output terminal. The control unit is configured to control a rising time required for a driving voltage for controlling the switching device to reach a target level such that a voltage between the control terminal and the output terminal is maintained less than or equal to a critical voltage. When the voltage between the control terminal and the output terminal is greater than the critical voltage, leakage current is generated between the control terminal and the output terminal.

摘要翻译： 功率器件包括开关器件和控制单元。 开关装置具有控制端子和输出端子。 控制单元被配置为控制用于控制开关器件达到目标电平的驱动电压所需的上升时间，使得控制端子和输出端子之间的电压保持小于或等于临界电压。 当控制端子与输出端子之间的电压大于临界电压时，控制端子与输出端子之间产生漏电流。

公开(公告)号：US20100309705A1

公开(公告)日：2010-12-09

申请号：US12662785

申请日：2010-05-04

申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

摘要翻译： 层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是 设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间 的多个存储器组。

公开(公告)号：US07495959B2

公开(公告)日：2009-02-24

申请号：US11605225

申请日：2006-11-29

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/24

摘要： A nonvolatile memory device includes a memory cell array and a voltage controller. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor connected in series between the first and second selection transistors. The voltage controller applies a first selection voltage to first selection lines connected to the first selection transistors, a second selection voltage to second selection lines connected to the second selection transistors, and a word line voltage to word lines connected to the memory cell transistors, in response to a plurality of block selection signals corresponding to the memory blocks. The voltage controller precharges the second selection lines to a precharge voltage by applying the second selection line voltage to the second selection lines in a standby state, where the second selection line voltage is equal to the precharge voltage.

摘要翻译： 非易失性存储器件包括存储单元阵列和电压控制器。 存储单元阵列包括多个存储块，每个存储块包括多个单元串，其中每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一和第二单元串之间的至少一个存储单元晶体管 选择晶体管。 电压控制器对连接到第一选择晶体管的第一选择线，连接到第二选择晶体管的第二选择线的第二选择电压和连接到存储单元晶体管的字线的字线电压施加第一选择电压， 响应于对应于存储块的多个块选择信号。 电压控制器通过在第二选择线电压等于预充电电压的待机状态下将第二选择线电压施加到第二选择线，将第二选择线预充电到预充电电压。