公开(公告)号：US07102184B2

公开(公告)日：2006-09-05

申请号：US10694990

申请日：2003-10-29

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L31/062

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14689 ,  H01L31/0352 ,  Y10S257/905

Abstract: The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation region. These dopant ions are further surrounded by dopant ions of the first conductivity type with a second impurity concentration. The resulting isolation region structure increases the capacitance of the photodiode by allowing the photodiode to possess a greater charge collection region while suppressing the generation of dark current.

Abstract translation: 本发明提供了具有增加的电荷收集区域的光电二极管，与相邻隔离区域横向间隔开。 具有第一杂质浓度的第一导电类型的掺杂离子形成围绕隔离区的至少一部分的区域。 这些掺杂剂离子还被具有第二杂质浓度的第一导电类型的掺杂剂离子进一步包围。 所得到的隔离区域结构通过允许光电二极管具有更大的电荷收集区域同时抑制暗电流的产生而增加了光电二极管的电容。

公开(公告)号：US07071531B2

公开(公告)日：2006-07-04

申请号：US10848389

申请日：2004-05-19

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L29/00

CPC classification number: H01L27/1463 ,  H01L21/76237 ,  H01L27/14643 ,  H01L27/14689

Abstract: A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

Abstract translation: 一种制造集成电路的方法包括在半导体衬底中形成隔离沟槽，并用电介质材料部分地填充沟槽，使得至少沟槽的侧壁被电介质材料涂覆。 在用介电材料部分地填充沟槽之后，将离子注入到隔离沟槽正下方的区域中的衬底中。 沿着沟槽的侧壁的电介质可以用作掩模，使得注入到隔离沟槽下方的基本上所有的离子从活性区域移位。 在离子注入到沟槽下方的衬底中之后，沟槽的其余部分可以用相同或另一种电介质材料填充。 沟槽隔离技术可用于制造可以显示减少的电流泄漏和/或减少的光学串扰的存储器，逻辑和成像器件。

公开(公告)号：US06998657B2

公开(公告)日：2006-02-14

申请号：US10688974

申请日：2003-10-21

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L27/148

CPC classification number: H01L27/14643 ,  H01L27/14689

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract translation: 通过减小每个像素单元中的栅极之间的间隙和/或通过在每个像素单元中的相邻栅极之间提供轻掺杂区域，特别是至少在电荷之间，在CMOS或CCD成像器中实现更完整的电荷转移 收集门和下游的门到电荷收集门。 为了减小栅极之间的间隙，在导电层上为每个栅极形成在其侧壁上具有间隔物的绝缘体盖。 然后使用绝缘体盖和间隔物作为硬掩模，从导电层蚀刻栅极，使得栅极能够形成得比先前可能的显着更靠近在一起，这又增加了电荷转移效率。 通过在相邻栅极之间提供轻掺杂区域，从电荷收集栅极实现更完整的电荷转移。

公开(公告)号：US06940112B2

公开(公告)日：2005-09-06

申请号：US10234351

申请日：2002-08-30

Applicant: Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

Inventor： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

IPC: C23C16/40 ,  H01L21/02 ,  H01L21/76

CPC classification number: H01L28/60 ,  C23C16/40 ,  H01L28/55 ,  H01L28/90

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract translation: 用于存储器件的电容器形成有用于底部电极的导电氧化物。 导电氧化物（RuO x S）在低温下作为非晶膜沉积。 结果，膜被共形沉积在三维折叠结构上。 此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。 沉积和抛光后，膜在非氧化环境中结晶。

公开(公告)号：US06927089B2

公开(公告)日：2005-08-09

申请号：US10345138

申请日：2003-01-16

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L27/146 ,  H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14645

Abstract: A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

Abstract translation: 公开了一种CMOS成像器，其具有形成在相应的像素传感器单元下方的多个渐变掺杂区域。 在半导体衬底的红色像素传感器单元下方形成深逆转p阱以增加红色响应。 在蓝色像素传感器单元下方形成浅的p阱，以减少红色和绿色响应，而在绿色像素传感器单元下方形成浅逆行p阱以增加绿色响应并降低红色响应。

公开(公告)号：US06869877B2

公开(公告)日：2005-03-22

申请号：US10234581

申请日：2002-08-30

Applicant: Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

Inventor： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

IPC: C23C16/40 ,  H01L21/02 ,  H01L21/44

CPC classification number: H01L28/60 ,  C23C16/40 ,  H01L28/55 ,  H01L28/90

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract translation: 用于存储器件的电容器形成有用于底部电极的导电氧化物。 导电氧化物（RuOx）在低温下作为非晶膜沉积。 结果，膜被共形沉积在三维折叠结构上。 此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。 沉积和抛光后，膜在非氧化环境中结晶。

公开(公告)号：US06852591B2

公开(公告)日：2005-02-08

申请号：US10132273

申请日：2002-04-26

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L21/02 ,  H01L27/146 ,  H01L21/8242

CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H01L28/90

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract translation: 公开了具有改善的信噪比和改善的动态范围的CMOS成像器。 CMOS成像器通过与成像器的光电收集区域并行地制造存储电容器来提供改进的电荷存储。 存储电容器可以是形成在像素上的平板电容器，形成在光电传感器中的层叠电容器或沟槽成像器。 因此，CMOS成像器具有更好的信噪比和改善的动态范围。 还公开了用于形成CMOS成像器的工艺。

公开(公告)号：US06844580B2

公开(公告)日：2005-01-18

申请号：US10361710

申请日：2003-02-11

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L27/146 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/14601 ,  H01L27/14636

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract translation: 形成为CMOS半导体集成电路的成像装置包括在浮动扩散区域和源极跟随器输出晶体管的栅极之间的埋置接触线。 CMOS成像器中的自对准埋入触点减少了从扩散区到衬底的泄漏，这可能与用于将扩散区与源极跟随器晶体管栅互连的其它技术发生。 此外，在浮动扩散区域和源极跟随器晶体管栅极之间最佳地形成自对准埋入触点，其允许源极跟随器晶体管放置得更靠近浮动扩散区域，从而允许在相同尺寸的成像器中的较大光电检测区域 电路。

公开(公告)号：US06821852B2

公开(公告)日：2004-11-23

申请号：US09782743

申请日：2001-02-13

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L218234

CPC classification number: H01L21/823892 ,  H01L21/2652 ,  H01L21/823842

Abstract: A method of forming an integrated circuit dual gate structure using only one mask is disclosed. In one embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having an NWELL is formed without using a mask, and a second gate structure having a PWELL is formed using only one mask. In an alternate embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having a PWELL is formed without using a mask, and a second gate structure having an NWELL is formed using only one mask.

Abstract translation: 公开了仅使用一个掩模形成集成电路双栅极结构的方法。 在一个实施例中，制备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有NWELL的第一栅极结构，并且仅使用一个掩模形成具有PWELL的第二栅极结构。 在替代实施例中，准备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有PWELL的第一栅极结构，并且仅使用一个掩模形成具有NWELL的第二栅极结构。

公开(公告)号：US06756616B2

公开(公告)日：2004-06-29

申请号：US09941546

申请日：2001-08-30

Applicant: Howard E. Rhodes

Inventor： Howard E. Rhodes

IPC: H01L31062

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14645

Abstract: A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

Abstract translation: 公开了一种CMOS成像器，其具有形成在相应的像素传感器单元下方的多个渐变掺杂区域。 在半导体衬底的红色像素传感器单元下方形成深逆转p阱以增加红色响应。 在蓝色像素传感器单元下方形成浅的p阱，以减少红色和绿色响应，而在绿色像素传感器单元下方形成浅逆行p阱以增加绿色响应并降低红色响应。