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    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
    4.
    发明申请
    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 审中-公开

    公开(公告)号：US20060076597A1

    公开(公告)日：2006-04-13

    申请号：US11235866

    申请日：2005-09-26

    申请人： Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    发明人： Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    IPC分类号： H01L29/94

    CPC分类号： H01L28/84 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

    摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

    Capacitor with high dielectric constant materials and method of making
    5.
    发明申请
    Capacitor with high dielectric constant materials and method of making 审中-公开
    具有高介电常数材料和制作方法的电容器

    公开(公告)号：US20060154382A1

    公开(公告)日：2006-07-13

    申请号：US11346676

    申请日：2006-02-03

    申请人： Cem Basceri ,  Gurtej Sandhu ,  Mark Visokay

    发明人： Cem Basceri ,  Gurtej Sandhu ,  Mark Visokay

    IPC分类号： H01L21/00 ,  H01L21/20

    CPC分类号： H01L28/56 ,  H01L27/10811

    摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1-x)TiO3, and methods of making such capacitors and DRAM cells are provided. One method includes providing a conductive oxide electrode, oxidizing at least the upper surface of the conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.

    摘要翻译： 使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元 ）和提供制造这种电容器和DRAM单元的方法。 一种方法包括提供导电氧化物电极，至少氧化导电氧化物电极的上表面，在导电氧化物电极上沉积高介电常数氧化物电介质材料的第一层，氧化高介电常数氧化物电介质的第一层 在氧化条件下的材料，在所述电介质的第一层上沉积高介电常数氧化物介电材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

    Capacitor with high dielectric constant materials and method of making
    6.
    发明授权
    Capacitor with high dielectric constant materials and method of making 失效
    具有高介电常数材料和制作方法的电容器

    公开(公告)号：US07037730B2

    公开(公告)日：2006-05-02

    申请号：US09904112

    申请日：2001-07-11

    申请人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

    发明人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/56 ,  H01L27/10811

    摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1−x)TiO3, and methods of making such capacitors and DRAM cells are provided. A preferred method includes providing a conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the conductive oxide electrode and the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.

    摘要翻译： 使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元 ）和提供制造这种电容器和DRAM单元的方法。 优选的方法包括提供导电氧化物电极，在导电氧化物电极上沉积高介电常数氧化物介电材料的第一层，在氧化条件下氧化导电氧化物电极和高介电常数氧化物介电材料的第一层，沉积 在所述电介质的第一层上的所述高介电常数氧化物电介质材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
    7.
    发明授权
    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 失效
    含有钌和钨的层的形成方法和集成电路结构

    公开(公告)号：US06833576B2

    公开(公告)日：2004-12-21

    申请号：US10002779

    申请日：2001-10-29

    申请人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    发明人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

    摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

    摘要翻译： 具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。 在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的， 产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。 初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。 该层可以形成在下面的导电层上。 处理可以在惰性环境或还原环境中进行。 可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。 氧化环境中的处理也可以进行以钝化粗糙层。 可以使用粗糙化的钌层来形成增强表面积的导电层。 所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。 在另一种方法中，提供氮化钨层作为这种电容器的第一电极。 电容器或至少氮化钨层被退火以增加电容器的电容。

    Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
    8.
    发明授权
    Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效

    公开(公告)号：US06812112B2

    公开(公告)日：2004-11-02

    申请号：US09965509

    申请日：2001-09-26

    申请人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

    发明人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

    IPC分类号： H01L218242

    CPC分类号： H01L28/82 ,  H01L28/55

    摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
    9.
    发明授权
    Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
    含有钌和钨的层的形成方法和集成电路结构

    公开(公告)号：US07253076B1

    公开(公告)日：2007-08-07

    申请号：US09590795

    申请日：2000-06-08

    申请人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    发明人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

    IPC分类号： H01L21/20

    CPC分类号： H01L28/84 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

    摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

    摘要翻译： 具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。 在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的， 产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。 初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。 该层可以形成在下面的导电层上。 处理可以在惰性环境或还原环境中进行。 可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。 氧化环境中的处理也可以进行以钝化粗糙层。 可以使用粗糙化的钌层来形成增强表面积的导电层。 所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。 在另一种方法中，提供氮化钨层作为这种电容器的第一电极。 电容器或至少氮化钨层被退火以增加电容器的电容。

    Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
    10.
    发明授权
    Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效
    包含增强表面积导电层的形成方法和集成电路结构

    公开(公告)号：US07253102B2

    公开(公告)日：2007-08-07

    申请号：US10860341

    申请日：2004-06-02

    申请人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

    发明人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L28/82 ,  H01L28/55

    摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

    摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。