公开(公告)号：US10554386B2

公开(公告)日：2020-02-04

申请号：US14014091

申请日：2013-08-29

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F12/0862 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10313107B2

公开(公告)日：2019-06-04

申请号：US14984616

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10270589B2

公开(公告)日：2019-04-23

申请号：US14572607

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: G06F21/72 ,  H04L9/28 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10263769B2

公开(公告)日：2019-04-16

申请号：US14984647

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10261795B2

公开(公告)日：2019-04-16

申请号：US15797524

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US10175990B2

公开(公告)日：2019-01-08

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US10171232B2

公开(公告)日：2019-01-01

申请号：US14984686

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: G06F21/72 ,  H04L9/28 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20180150301A9

公开(公告)日：2018-05-31

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US09740489B2

公开(公告)日：2017-08-22

申请号：US14562632

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Method, apparatus, and program for performing a comparison operation. The apparatus includes execution resources to execute a first instruction. In response to the first instruction, the execution resources store a result of a comparison between valid data element of a first and second operand.

公开(公告)号：US09720692B2

公开(公告)日：2017-08-01

申请号：US14562641

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Method, apparatus, and program for performing a comparison operation. An apparatus includes execution resources to execute a first instruction. In response to the first instruction, the execution resources store a result of a comparison between valid data elements of a first and second operand.