公开(公告)号：US10425358B2

公开(公告)日：2019-09-24

申请号：US15279805

申请日：2016-09-29

Applicant: International Business Machines Corporation

Inventor： Dong Chen ,  Philip Heidelberger ,  Craig Stunkel

IPC: H04L12/933 ,  H04L12/935

Abstract: An apparatus includes a collective switch hardware architecture, including an input arrangement circuit including multiple input ports and multiple outputs. The input arrangement circuit routes its multiple input ports to selected ones of its outputs. The collective switch hardware architecture includes collective reduction logic coupled to the multiple outputs of the input arrangement circuit and having multiple outputs. The collective reduction logic includes ALU(s) and arbitration and control circuitry. The ALU(s) and arbitration and control circuitry support multiple simultaneous collective operations from different collective classes, and support arbitrary input port and output port mapping to different collective classes. The collective switch hardware architecture further includes an output arrangement circuit including a multiple inputs coupled to the multiple outputs of the collective reduction logic and including multiple output ports. The output arrangement circuit is configured to route its multiple inputs to selected ones of its output ports.

公开(公告)号：US20180357228A1

公开(公告)日：2018-12-13

申请号：US15617081

申请日：2017-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dong Chen ,  Ling Chen ,  Jie Peng ,  Li Ni Zhang ,  Min Min Zhou

IPC: G06F17/30

Abstract: A method and system for improving a data storage system is provided. The method includes extracting original data storage attributes from metadata comprised by data for storage within a hardware storage system. Additional data storage attributes associated with current storage requirements of the data are retrieved and merged with the original data storage attributes resulting in a group of combined data storage attributes. An attribute matrix categorizing attribute types each attribute is generated. A digital tag defining the attribute matrix is generated and attached to the metadata. Data storage tier definitions and associated tier attributes are received and associated with the digital tag. Resulting specified tiers of the hardware storage system a defined for storage of specified portions of the data and each portion of data is stored within an associated tier.

公开(公告)号：US10069599B2

公开(公告)日：2018-09-04

申请号：US14972945

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

IPC: G06F15/16 ,  H04L1/08 ,  H03M13/09 ,  G06F9/46 ,  G06F11/08 ,  G06F11/14 ,  H04L1/00 ,  H04L1/16 ,  H04L1/18

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

公开(公告)号：US20170195212A1

公开(公告)日：2017-07-06

申请号：US14985027

申请日：2015-12-30

Applicant: International Business Machines Corporation

Inventor： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar

IPC: H04L12/761 ,  H04L29/06 ,  G06F3/06

CPC classification number: H04L45/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/067 ,  H04L69/22

Abstract: A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.

公开(公告)号：US09699078B1

公开(公告)日：2017-07-04

申请号：US14982547

申请日：2015-12-29

Applicant: International Business Machines Corporation

Inventor： Dong Chen ,  Philip Heidelberger ,  Yutaka Sugawara

IPC: H04L12/771 ,  H04L12/775 ,  H04L12/46 ,  H04L12/715

CPC classification number: H04L45/583 ,  H04L12/46 ,  H04L41/12 ,  H04L45/04

Abstract: An apparatus and method for extending the scalability and improving the partitionability of networks that contain all-to-all links for transporting packet traffic from a source endpoint to a destination endpoint with low per-endpoint (per-server) cost and a small number of hops. An all-to-all wiring in the baseline topology is decomposed into smaller all-to-all components in which each smaller all-to-all connection is replaced with star topology by using global switches. Stacking multiple copies of the star topology baseline network creates a multi-planed switching topology for transporting packet traffic. Point-to-point unified stacking method using global switch wiring methods connects multiple planes of a baseline topology by using the global switches to create a large network size with a low number of hops, i.e., low network latency. Grouped unified stacking method increases the scalability (network size) of a stacked topology.

公开(公告)号：US08943350B2

公开(公告)日：2015-01-27

申请号：US13693894

申请日：2012-12-04

Applicant: International Business Machines Corporation

Inventor： Dong Chen ,  Daniel A. Faraj ,  Thomas M. Gooding ,  Philip Heidelberger

IPC: G06F1/12

CPC classification number: G06F1/12 ,  H04L12/413

Abstract: Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.

Abstract translation: 在并行计算机中同步时基，其包括为树网络中的数据通信而组织的计算节点，其中一个计算节点被指定为根，并且对于每个计算节点，计算从根到计算节点的数据传输等待时间; 将线程配置为脉冲服务员; 初始化唤醒单元; 并执行局部屏障操作; 在每个节点完成局部屏障操作时，由所有计算节点进入全局屏障操作; 在所有节点进入全局屏障操作之后，向所有计算节点发送脉冲信号; 并且对于每个计算节点在接收到脉冲信号时：由唤醒单元唤醒脉冲服务员; 为计算节点设置等于根节点和计算节点之间的数据传输延迟的时基; 并退出全球屏障操作。

公开(公告)号：US08856261B2

公开(公告)日：2014-10-07

申请号：US13729937

申请日：2012-12-28

Applicant: International Business Machines Corporation

Inventor： Dong Chen ,  Philip Heidelberger

IPC: G06F15/167 ,  G06F11/00 ,  G06F7/38

CPC classification number: G06F15/167 ,  G06F11/141

Abstract: A system, method and computer program product for supporting system initiated checkpoints in parallel computing systems. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity.

Abstract translation: 一种用于在并行计算系统中支持系统启动的检查点的系统，方法和计算机程序产品。 系统和方法产生选择性控制信号，以在存在与在节点处运行的用户应用相关联的消息传送活动的情况下执行系统相关数据的检查点。 检查点由系统启动，使得即使在存在包括正在进行的用户消息活动的高度并行计算机上的用户应用的情况下，也可以获得多个网络节点的检查点数据。

公开(公告)号：US20140122980A1

公开(公告)日：2014-05-01

申请号：US14148348

申请日：2014-01-06

Applicant: International Business Machines Corporation

Inventor： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd Takken ,  Burkhard Steinmacher-Burow ,  Pavlos M. Vranas

IPC: G06F11/08 ,  G06F9/46

CPC classification number: H04L1/08 ,  G06F9/46 ,  G06F11/08 ,  G06F11/1423 ,  H03M13/09 ,  H04L1/0061 ,  H04L1/1607 ,  H04L1/1867 ,  H04L2001/0093 ,  H04L2001/0097

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract translation: 一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。 全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。 包括通过链路互连网络节点的路由器设备，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。 全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。 当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

公开(公告)号：US20240348467A1

公开(公告)日：2024-10-17

申请号：US18301028

申请日：2023-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dong Chen ,  Yuan Jie Zhang ,  Ming Lei Zhang ,  Yin Xi Guo ,  Ting Ting Zhan

IPC: H04L12/18

CPC classification number: H04L12/1831 ,  H04L12/1822

Abstract: A method, computer system, and a computer program product are provided for a restoring missing content to a user that was absent during a portion of a live event. The process will identify the absence period and that is being participated by a user and obtains extracted information relating to the user that was previously gathered from a variety of sources including past user interactions and a user profile. This information is further analyzed and prioritized according to user interest priority determined by the extracted information. This information is categorized into a first set of domains. Information provided during the absence of the user will also be captured and categorized into a second set of domain categories. An intersection between the first and second set of domain categories will be found and prioritized by user interest. This will be presented to the user upon user's return.

公开(公告)号：US11409918B1

公开(公告)日：2022-08-09

申请号：US17242339

申请日：2021-04-28

Applicant: International Business Machines Corporation

Inventor： Krishnan Sugavanam ,  Sandhya Koteshwara ,  Dong Chen

IPC: G06F21/85 ,  G06F21/57 ,  G06F21/64

Abstract: Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.