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1.发明申请公开(公告)号：US20190208624A1
公开(公告)日：2019-07-04
申请号：US15858432
申请日：2017-12-29
发明人： Paul W. Coteus , Andrew Ferencz , Todd Takken , Yuan Yao , Xin Zhang
CPC分类号： H05K1/0265 , H01F27/06 , H01F27/24 , H01F27/28 , H01F2027/065 , H05K1/165
摘要： An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.
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公开(公告)号：US20140136770A1
公开(公告)日：2014-05-15
申请号：US14160590
申请日：2014-01-22
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage with low latency is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译： 具有低延迟的持久数据存储由计算机程序产品提供，计算机程序产品包括被配置用于接收包括写入数据的低延迟存储命令的计算机程序代码。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。
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公开(公告)号：US11056413B2
公开(公告)日：2021-07-06
申请号：US16417845
申请日：2019-05-21
发明人： Xin Zhang , Todd Takken , Shurong Tian , Yuan Yao
IPC分类号： H01L49/02 , H01L23/64 , H01L23/367
摘要： An inductor includes a conductor having a first end and a second end, wherein the first end, the second end, or both ends are configured to be mounted on a substrate and configured to receive a heat flow; and one or more magnetic cores surrounding a first portion of the conductor, the first portion of the conductor being intermediate the first end and the second end of the conductor. A second portion of the conductor not surrounded by the one or more magnetic cores is configured to transfer the heat flow from the conductor.
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公开(公告)号：US10972083B2
公开(公告)日：2021-04-06
申请号：US16359664
申请日：2019-03-20
发明人： Xin Zhang , Todd Takken , Tianyu Jia
摘要： Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.
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5.发明授权Error recovery to enable error-free message transfer between nodes of a computer network 有权错误恢复，使计算机网络的节点之间无差错的消息传输公开(公告)号：US09244759B2
公开(公告)日：2016-01-26
申请号：US14148348
申请日：2014-01-06
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd Takken , Burkhard Steinmacher-Burow , Pavlos M. Vranas
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.
摘要翻译： 一种错误恢复方法，可在计算机网络的节点之间实现无错误的消息传输。 网络的第一节点通过节点之间的链路将分组发送到网络的第二节点，并且第一节点在链路的发送端保持分组的副本，直到第一节点从第二节点接收到确认 该数据包被收到没有错误。 第二个节点测试数据包以确定数据包是否无错误。 如果数据包不是无错误的，则第二个节点设置一个标志，以将数据包标记为已损坏。 第二个节点向第一个节点返回确认，指定该数据包是否被接收到有或没有错误。 当分组被接收到错误时，链路返回到已知状态，并且分组被再次发送到第二节点。
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公开(公告)号：US20200373217A1
公开(公告)日：2020-11-26
申请号：US16417845
申请日：2019-05-21
发明人： Xin Zhang , Todd Takken , Shurong Tian , Yuan Yao
IPC分类号： H01L23/367 , H01L23/64 , H01L49/02
摘要： An inductor includes a conductor having a first end and a second end, wherein the first end, the second end, or both ends are configured to be mounted on a substrate and configured to receive a heat flow; and one or more magnetic cores surrounding a first portion of the conductor, the first portion of the conductor being intermediate the first end and the second end of the conductor. A second portion of the conductor not surrounded by the one or more magnetic cores is configured to transfer the heat flow from the conductor.
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公开(公告)号：US20200304112A1
公开(公告)日：2020-09-24
申请号：US16359664
申请日：2019-03-20
发明人： Xin Zhang , Todd Takken , Tianyu Jia
摘要： Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.
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公开(公告)号：US08880834B2
公开(公告)日：2014-11-04
申请号：US14160590
申请日：2014-01-22
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译： 持续数据存储由计算机程序产品提供，该计算机程序产品包括被配置用于接收包括写入数据的低延迟存储命令的计算机程序代码。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。
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公开(公告)号：US20140122980A1
公开(公告)日：2014-05-01
申请号：US14148348
申请日：2014-01-06
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd Takken , Burkhard Steinmacher-Burow , Pavlos M. Vranas
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译： 一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。 全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。 包括通过链路互连网络节点的路由器设备，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。 全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。 当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。
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10.发明授权公开(公告)号：US10939543B2
公开(公告)日：2021-03-02
申请号：US15858432
申请日：2017-12-29
发明人： Paul W Coteus , Andrew Ferencz , Todd Takken , Yuan Yao , Xin Zhang
摘要： An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.
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