公开(公告)号：US20190164969A1

公开(公告)日：2019-05-30

申请号：US15859356

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Jeffrey S. LEIB ,  Jenny HU ,  Anindya DASGUPTA ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

公开(公告)号：US20190164841A1

公开(公告)日：2019-05-30

申请号：US15859411

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US20190164818A1

公开(公告)日：2019-05-30

申请号：US15859417

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ruth BRAIN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

公开(公告)号：US20190164809A1

公开(公告)日：2019-05-30

申请号：US15859323

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Heidi M. MEYER ,  Ahmet TURA ,  Byron HO ,  Subhash JOSHI ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.