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公开(公告)号:US20240038578A1
公开(公告)日:2024-02-01
申请号:US18376763
申请日:2023-10-04
Applicant: Intel Corporation
Inventor: Heidi M. MEYER , Ahmet TURA , Byron HO , Subhash JOSHI , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L29/78 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L27/088 , H10B10/00
CPC classification number: H01L21/76224 , H01L28/24 , H01L21/823481 , H01L21/823431 , H01L21/823878 , H01L21/823807 , H01L21/823821 , H01L21/31144 , H01L21/31105 , H01L29/0847 , H01L29/7843 , H01L29/7846 , H01L29/6653 , H01L21/3086 , H01L27/0924 , H01L29/516 , H01L21/823857 , H01L21/823842 , H01L21/823814 , H01L21/823871 , H01L21/28568 , H01L21/28247 , H01L21/0337 , H01L21/76816 , H01L23/53238 , H01L23/53266 , H01L23/5226 , H01L23/5283 , H01L29/7854 , H01L29/66795 , H01L29/7848 , H01L29/66818 , H01L27/0886 , H01L29/785 , H10B10/12
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
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公开(公告)号:US20220068907A1
公开(公告)日:2022-03-03
申请号:US16950042
申请日:2020-11-17
Applicant: Intel Corporation
Inventor: Ahmet TURA , Steven G. JALOVIAR
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.
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公开(公告)号:US20220406650A1
公开(公告)日:2022-12-22
申请号:US17890969
申请日:2022-08-18
Applicant: Intel Corporation
Inventor: Heidi M. MEYER , Ahmet TURA , Byron HO , Subhash JOSHI , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/762 , H01L49/02 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/78 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L27/088
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
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公开(公告)号:US20190164809A1
公开(公告)日:2019-05-30
申请号:US15859323
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Heidi M. MEYER , Ahmet TURA , Byron HO , Subhash JOSHI , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/762 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L49/02
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
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