公开(公告)号：US20070081516A1

公开(公告)日：2007-04-12

申请号：US11245887

申请日：2005-10-07

申请人： Ravi Arimilli ,  Benjiman Goodman ,  Guy Guthrie ,  Praveen Reddy ,  William Starke

发明人： Ravi Arimilli ,  Benjiman Goodman ,  Guy Guthrie ,  Praveen Reddy ,  William Starke

IPC分类号： H04L12/28

CPC分类号： G06F15/16

摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.

摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。

公开(公告)号：US20060187958A1

公开(公告)日：2006-08-24

申请号：US11055399

申请日：2005-02-10

申请人： Leo Clark ,  Guy Guthrie ,  William Starke

发明人： Leo Clark ,  Guy Guthrie ,  William Starke

IPC分类号： H04J3/22 ,  H04J3/16

CPC分类号： H04L47/722 ,  H04L47/70 ,  H04L49/109

摘要： A data processing system includes a plurality of local hubs each coupled to a remote hub by a respective one a plurality of point-to-point communication links. Each of the plurality of local hubs queues requests for access to memory blocks for transmission on a respective one of the point-to-point communication links to a shared resource in the remote hub. Each of the plurality of local hubs transmits requests to the remote hub utilizing only a fractional portion of a bandwidth of its respective point-to-point communication link. The fractional portion that is utilized is determined by an allocation policy based at least in part upon a number of the plurality of local hubs and a number of processing units represented by each of the plurality of local hubs. The allocation policy prevents overruns of the shared resource.

摘要翻译： 数据处理系统包括多个本地集线器，每个集线器通过相应的一个多个点对点通信链路耦合到远程集线器。 多个本地集线器中的每一个排队对存储器块进行访问的请求，用于在到远程集线器中的共享资源的点对点通信链路中的相应一个上传输。 多个本地集线器中的每一个仅利用其相应点对点通信链路的带宽的小数部分向远程集线器发送请求。 所使用的分数部分由至少部分地基于多个本地集线器的数量和由多个本地集线器中的每一个表示的多个处理单元的分配策略确定。 分配策略可以防止超出共享资源。

公开(公告)号：US20060179244A1

公开(公告)日：2006-08-10

申请号：US11055418

申请日：2005-02-10

申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

摘要翻译： 高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。 第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。 响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。 响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。

公开(公告)号：US20060179223A1

公开(公告)日：2006-08-10

申请号：US11054930

申请日：2005-02-10

申请人： Leo Clark ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

发明人： Leo Clark ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0822 ,  G06F12/0824

摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

摘要翻译： 缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行 。 优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。 在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中 并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。 可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。 给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。 例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个 四个周期。

公开(公告)号：US20060085605A1

公开(公告)日：2006-04-20

申请号：US10965151

申请日：2004-10-14

申请人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

公开(公告)号：US20060179252A1

公开(公告)日：2006-08-10

申请号：US11055305

申请日：2005-02-10

申请人： Jason Cantin ,  James Fields ,  Steven Kunkel ,  William Starke

发明人： Jason Cantin ,  James Fields ,  Steven Kunkel ,  William Starke

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。 数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。 相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

公开(公告)号：US20060184836A1

公开(公告)日：2006-08-17

申请号：US11055977

申请日：2005-02-11

申请人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

发明人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/3476 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。

公开(公告)号：US20070073998A1

公开(公告)日：2007-03-29

申请号：US11236458

申请日：2005-09-27

申请人： Vicente Chung ,  Benjiman Goodman ,  Praveen Reddy ,  William Starke

发明人： Vicente Chung ,  Benjiman Goodman ,  Praveen Reddy ,  William Starke

IPC分类号： G06F15/00

CPC分类号： G06F15/17337

摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.

摘要翻译： 数据处理系统包括第一处理节点和第二处理节点。 第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。 多个第一处理单元中的每一个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。

公开(公告)号：US20060184834A1

公开(公告)日：2006-08-17

申请号：US11055845

申请日：2005-02-11

申请人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

发明人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

公开(公告)号：US20060184833A1

公开(公告)日：2006-08-17

申请号：US11055821

申请日：2005-02-11

申请人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

发明人： Ra'ed Al-Omari ,  Alexander Mericas ,  William Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

摘要翻译： 公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的方法，装置和计算机程序产品。 处理器包括利用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 利用系统总线在处理单元之间传送信息。 信息根据标准系统总线协议进行格式化。 使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。 系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。 存储器控制器直接耦合到系统总线。 硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。