公开(公告)号：US20060184772A1

公开(公告)日：2006-08-17

申请号：US11055862

申请日：2005-02-11

申请人： Miles Dooley ,  Scott Frommer ,  Hung Le ,  Sheldon Levenstein ,  Anthony Saporito

发明人： Miles Dooley ,  Scott Frommer ,  Hung Le ,  Sheldon Levenstein ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.

摘要翻译： 一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。 特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

公开(公告)号：US20060184771A1

公开(公告)日：2006-08-17

申请号：US11055823

申请日：2005-02-11

申请人： Michael Floyd ,  Larry Leitner ,  Sheldon Levenstein ,  Scott Swaney ,  Brian Thompto

发明人： Michael Floyd ,  Larry Leitner ,  Sheldon Levenstein ,  Scott Swaney ,  Brian Thompto

IPC分类号： G06F9/30

CPC分类号： G06F9/3863 ,  G06F9/3851

摘要： A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions.

摘要翻译： 一种用于避免微处理器设计缺陷并由于设计缺陷而使微处理器故障恢复的数据处理系统中的方法，该方法包括以下步骤：该方法检测并报告发生错误的事件。 然后，该方法锁定当前的检查点状态，并防止从检查点进行检查点的指令。 之后，该方法将检查点状态存储发送到L2缓存，并且将不检查点丢弃存储。 接下来，该方法将阻止中断，直到恢复完成。 然后该方法将禁用整个处理器的省电状态。 之后，该方法禁用指令提取和指令分派。 接下来，该方法发送硬件复位信号。 然后，该方法将从当前检查点状态恢复所选寄存器。 接下来，该方法从恢复的指令地址获取指令。 然后，该方法在可编程指令数量之后恢复正常执行。

公开(公告)号：US20060184734A1

公开(公告)日：2006-08-17

申请号：US11055828

申请日：2005-02-11

申请人： Eric Fluhr ,  Sheldon Levenstein

发明人： Eric Fluhr ,  Sheldon Levenstein

IPC分类号： G06F12/00

CPC分类号： G06F12/04 ,  G06F12/0846 ,  G06F12/0886

摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

摘要翻译： 一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。 通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地 地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。 这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

公开(公告)号：US20060179266A1

公开(公告)日：2006-08-10

申请号：US11054274

申请日：2005-02-09

申请人： Rachel Flood ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein ,  Michael Vaden

发明人： Rachel Flood ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein ,  Michael Vaden

IPC分类号： G06F12/00

CPC分类号： G06F9/355 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1027

摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

公开(公告)号：US20060179258A1

公开(公告)日：2006-08-10

申请号：US11054262

申请日：2005-02-09

申请人： Miles Dooley ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein

发明人： Miles Dooley ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein

IPC分类号： G06F12/10

CPC分类号： G06F11/362

摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.

公开(公告)号：US20060085605A1

公开(公告)日：2006-04-20

申请号：US10965151

申请日：2004-10-14

申请人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

公开(公告)号：US20060179264A1

公开(公告)日：2006-08-10

申请号：US11054277

申请日：2005-02-09

申请人： Joaquin Hinojosa ,  Sheldon Levenstein ,  Bruce Ronchetti

发明人： Joaquin Hinojosa ,  Sheldon Levenstein ,  Bruce Ronchetti

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.

摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

公开(公告)号：US20060085604A1

公开(公告)日：2006-04-20

申请号：US10965144

申请日：2004-10-14

申请人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Sheldon Levenstein ,  William Starke ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0855

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。

公开(公告)号：US20060002163A1

公开(公告)日：2006-01-05

申请号：US10880719

申请日：2004-06-30

申请人： Michael Ju Lee ,  Sheldon Levenstein ,  Edelmar Seewann

发明人： Michael Ju Lee ,  Sheldon Levenstein ,  Edelmar Seewann

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

摘要翻译： 公开了用于检测CAM阵列中的多个命中的装置和方法。 为CAM阵列的每个条目存储二进制地址值，并输出以识别单个命中的匹配条目。 然而，为了便于多次命中检测，存储和输出该地址的真实和补码成分，以确定是否发生多次命中。 如果发生多重命中（例如，多于一个地址位置已匹配），构成二进制地址和补码的所有位将不会互相补充，并且可以通过将每个位的异或来检测多个命中条件 具有该地址位置值的补码的地址位置值。 如果异或位等于“1”，则发生单击。 否则，发生多重命中。

公开(公告)号：US20080104599A1

公开(公告)日：2008-05-01

申请号：US11969988

申请日：2008-01-07

申请人： Joaquin Hinojosa ,  Sheldon Levenstein ,  Bruce Ronchetti

发明人： Joaquin Hinojosa ,  Sheldon Levenstein ,  Bruce Ronchetti

IPC分类号： G06F9/46

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.

摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。