公开(公告)号：US20110068436A1

公开(公告)日：2011-03-24

申请号：US12566043

申请日：2009-09-24

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/311 ,  H01L21/3213 ,  H01L23/544

CPC classification number: H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3185

Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.

Abstract translation: 用于增强不同基底区域中异质特征之间的周长与表面积之比的均匀性的方法和结构。 衬底上的至少一种形状包括有效减少第一衬底区域中的特征与第二衬底区域中的特征之间的周边表面积比的差异的附加边缘。 周边至表面积比的改善的均匀性降低了跨越第一和第二基底区域中的特征沉积的共形层的厚度变化。

公开(公告)号：US07900178B2

公开(公告)日：2011-03-01

申请号：US12039109

申请日：2008-02-28

Applicant: James A. Culp ,  Gregory A. Northrop ,  Ming Yin

Inventor： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract translation: 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部表示或内部视图包括形成细胞组分的规则形状，并定义细胞结构细节，并通过构造进行基础规则清洁或通过模拟或硬件验证。

公开(公告)号：US20100261351A1

公开(公告)日：2010-10-14

申请号：US12622557

申请日：2009-11-20

Applicant: James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Paterson ,  Jed H. Rankin

Inventor： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Paterson ,  Jed H. Rankin

IPC: H01L21/302 ,  H01L21/306

CPC classification number: H01L21/31144

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract translation: 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

公开(公告)号：US07565633B2

公开(公告)日：2009-07-21

申请号：US11619320

申请日：2007-01-03

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.

Abstract translation: 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。

公开(公告)号：US20090125868A1

公开(公告)日：2009-05-14

申请号：US12357648

申请日：2009-01-22

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Abstract translation: 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

公开(公告)号：US07450748B2

公开(公告)日：2008-11-11

申请号：US10725854

申请日：2003-12-02

Applicant: Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

Inventor： Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

IPC: G06K9/00

CPC classification number: G03F7/70441

Abstract: A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S′ upon being printed. At least one of the shapes S′ may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S″ approximating the shapes S′. A geometric distortion between the shapes S′ and S″ is less than a corresponding geometric distortion between the shapes S′ and S.

Abstract translation: 面罩检查方法和系统。 提供了一种掩模制造数据库，其描述要在掩模版上作为掩模图案的一部分打印的几何形状S，以通过使用掩模制造工具来制造掩模。 形状S在印刷时作为形状S'出现在掩模上。 由于在掩模制造工具中缺乏精度，至少一种形状S'可能相对于形状S中的相应的至少一个形状几何失真。 还提供了掩模检查数据库，用于在通过掩模制造工具制造掩模之后检查掩模。 掩模检查数据库描述形状S'近似形状S'。 形状S'和S“之间的几何变形小于形状S'和S之间的对应的几何变形。

公开(公告)号：US20080155482A1

公开(公告)日：2008-06-26

申请号：US11614260

申请日：2006-12-21

Applicant: Dureseti Chidambarrao ,  James A. Culp ,  Jason D. Hibbeler

Inventor： Dureseti Chidambarrao ,  James A. Culp ,  Jason D. Hibbeler

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: VLSI lithographic fidelity is improved via reducing the pattern space of difficult patterns or structures in a design layout for an integrated circuit design, and thereby increasing the regularity of the design, by converting patterns or structures that are similar but not identical to one another into a smaller set of canonical geometric configurations. By doing so, lithographic processing can be tuned to handle the smaller set of configurations more accurately and efficiently.

Abstract translation: 通过在集成电路设计的设计布局中减少难图案或结构的图案空间来改进VLSI光刻保真度，从而通过将彼此相似但不完全相同的图案或结构转换为 较小的规范几何配置。 通过这样做，可以调整光刻处理以更准确和有效地处理较小的一组配置。

公开(公告)号：US06892365B2

公开(公告)日：2005-05-10

申请号：US10249524

申请日：2003-04-16

Applicant: James A. Culp ,  Mark A. Lavin ,  Robert T. Sayah

Inventor： James A. Culp ,  Mark A. Lavin ,  Robert T. Sayah

IPC: H01L21/027 ,  G06F17/50

CPC classification number: G06F17/5081

Abstract: A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.

Abstract translation: 预测半导体晶片的相邻的，光刻制造的层上的电路配置的覆盖失效的方法包括提供在半导体晶片的一个或多个相邻层上光刻制造的电路部分的设计配置，然后预测每个电路的形状和对准 每个相邻层上的部分使用用于过程波动或未对准误差的一个或多个预定值。 然后，该方法确定预测形状和电路部分的对准的重叠的尺寸，并将确定的重叠尺寸与理论最小值进行比较，以确定重叠的预测尺寸是否失败。 使用不同的过程波动值和未对准误差值，然后对提供的设计配置迭代重复这些步骤，以确定重叠的预测维度是否失败，并报告故障的测量。