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    INTEGRATED CIRCUIT (IC) DESIGN METHOD, SYSTEM AND PROGRAM PRODUCT
    1.
    发明申请
    INTEGRATED CIRCUIT (IC) DESIGN METHOD, SYSTEM AND PROGRAM PRODUCT 有权
    集成电路（IC）设计方法，系统和程序产品

    公开(公告)号：US20090222783A1

    公开(公告)日：2009-09-03

    申请号：US12039109

    申请日：2008-02-28

    申请人： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

    发明人： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

    摘要翻译： 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部电池或内部视图包括形成电池组件的规则形状，并定义电池构造细节，并通过构造进行接地规则清洁，或通过仿真或硬件验证。

    Integrated circuit (IC) design method, system and program product
    2.
    发明授权
    Integrated circuit (IC) design method, system and program product 有权
    集成电路（IC）设计方法，系统和程序产品

    公开(公告)号：US07900178B2

    公开(公告)日：2011-03-01

    申请号：US12039109

    申请日：2008-02-28

    申请人： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

    发明人： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

    摘要翻译： 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部表示或内部视图包括形成细胞组分的规则形状，并定义细胞结构细节，并通过构造进行基础规则清洁或通过模拟或硬件验证。

    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
    8.
    发明申请
    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
    参数化分析与管理方法与系统

    公开(公告)号：US20120227019A1

    公开(公告)日：2012-09-06

    申请号：US13471789

    申请日：2012-05-15

    申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    IPC分类号： G06F17/50

    CPC分类号： G01R31/26 ,  G06F17/5045

    摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

    摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

    Multilayer OPC for design aware manufacturing
    9.
    发明授权
    Multilayer OPC for design aware manufacturing 有权
    多层OPC用于设计感知制造

    公开(公告)号：US08214770B2

    公开(公告)日：2012-07-03

    申请号：US12357648

    申请日：2009-01-22

    申请人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    发明人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

    摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE
    10.
    发明申请
    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE 失效
    分析多种诱导系统和统计布局对电路性能的依赖性影响

    公开(公告)号：US20120144356A1

    公开(公告)日：2012-06-07

    申请号：US13371537

    申请日：2012-02-13

    申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5009 ,  G06F2217/10

    摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

    摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。