公开(公告)号：US20060172190A1

公开(公告)日：2006-08-03

申请号：US11045900

申请日：2005-01-28

Applicant: David Kaplin ,  James Wu

Inventor： David Kaplin ,  James Wu

IPC: H01M2/26 ,  H01M2/02

CPC classification number: H01M2/266 ,  H01M2/02 ,  H01M2/263 ,  H01M10/0525 ,  H01M10/058

Abstract: An electrochemical battery cell with an electrical lead for electrical contact between one of the cell's electrodes and the side of the cell container. A portion of the lead, disposed between the electrode assembly and the side wall of the container, includes an initially non-planar shape that is in a partially deformed, compressed configuration within the cell to bias the lead against the internal surface of the side wall of the container, thereby applying sufficient force to provide good electrical contact between the electrode and the container. The initially non-planar shape can include one or more V-shaped or arc-shaped grooves, and the grooves can be disposed parallel to a longitudinal axis of the electrode assembly. Also disclosed is a process for making such a cell.

公开(公告)号：US06983442B1

公开(公告)日：2006-01-03

申请号：US10649401

申请日：2003-08-26

Applicant: Steven J. E. Wilton ,  Kimberly Bozman ,  Noha Kafafi ,  James Wu

Inventor： Steven J. E. Wilton ,  Kimberly Bozman ,  Noha Kafafi ,  James Wu

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.

Abstract translation: 具有固定和可编程逻辑部分的集成电路装置通过组合固定逻辑的硬件描述语言表示和可编程逻辑的硬件描述语言表示来创建设备的单个硬件描述语言表示。 这允许可编程逻辑的多个部分，分布在需要的任何大小的所需尺寸上，以分散在固定逻辑中。 由于可编程逻辑（而不是用户编程）的行为被表示，所以提供了一种可编程逻辑体系结构，其缺少行为，例如组合循环，这将导致硬件描述语言的编译以产生错误。

公开(公告)号：US20050243176A1

公开(公告)日：2005-11-03

申请号：US10834881

申请日：2004-04-30

Applicant: James Wu ,  Tsung-Wei Lin

Inventor： James Wu ,  Tsung-Wei Lin

IPC: G06T5/50 ,  H04N1/387 ,  H04N1/407 ,  H04N5/225

CPC classification number: H04N1/3871 ,  G06T5/50 ,  H04N1/4072 ,  H04N5/2355

Abstract: A method of HDR image processing and manipulation, including the steps of displaying a first control element for loading of multiple files containing pixel values of differently exposed LDR images, and metadata information including exposure times of the LDR images, displaying thumbnails of the LDR images sorted by the exposure times, displaying a second control element for automatic creation of a camera response function using the pixel values and the exposure times, displaying a first setting element for acquisition of an overall contrast and a set of values determining a first mapping function, and displaying a third control element for construction and displaying of an HDR radiance map by contrast reduction and tone mapping adjustment.

Abstract translation: 一种HDR图像处理和操作的方法，包括以下步骤：显示用于加载包含不同曝光的LDR图像的像素值的多个文件的第一控制元素，以及包括LDR图像的曝光时间的元数据信息，显示分类的LDR图像的缩略图 通过曝光时间，显示用于使用像素值和曝光时间自动创建相机响应功能的第二控制元件，显示用于获取整体对比度的第一设置元素和确定第一映射功能的一组值，以及 通过对比度降低和色调映射调整显示用于构造和显示HDR辐射图的第三控制元件。

公开(公告)号：US20050142026A1

公开(公告)日：2005-06-30

申请号：US11015129

申请日：2004-12-17

Applicant: James Wu ,  Matthew Yao

Inventor： James Wu ,  Matthew Yao

IPC: C22C19/07

CPC classification number: C22C19/07 ,  B22F3/115 ,  B22F7/04 ,  B22F7/08 ,  C23C2/003 ,  C23C4/04 ,  C23C4/12 ,  C23C30/00

Abstract: A Co—Mo—Cr Co-based alloy and overlay for wear and corrosion applications. The Mo:Si ratio is between about 15:1 and about 22:1 for enhanced ductility with a Laves phase.

Abstract translation: Co-Mo-Cr Co基合金和覆盖层用于磨损和腐蚀应用。 Mo：Si比为约15：1至22：1，以提高Laves相的延展性。

公开(公告)号：USD505482S1

公开(公告)日：2005-05-24

申请号：US29196368

申请日：2003-12-26

Applicant: James Wu

Designer： James Wu

公开(公告)号：USD497196S1

公开(公告)日：2004-10-12

申请号：US29190537

申请日：2003-09-16

Applicant: James Wu ,  Hank Her

Designer： James Wu ,  Hank Her

公开(公告)号：US06622945B1

公开(公告)日：2003-09-23

申请号：US10374204

申请日：2003-02-27

Applicant: James Wu ,  Len Gen Yan

Inventor： James Wu ,  Len Gen Yan

IPC: A62C3100

CPC classification number: B05B1/1654

Abstract: A shower head structure, comprising a body, a front housing, a push button, a water guide member, a flow switch disk, a first water outlet panel, a second water outlet panel, and a third water outlet panel. Thus, the user can operate the push button by his one hand only, so as to switch and adjust the water flow, thereby facilitating the user switching and adjusting the water flow of the shower head. In addition, the user can press the push button to switch and adjust the water flow through the first water outlet panel, the second water outlet panel and the third water outlet panel, thereby enhancing the versatility of the shower head.

Abstract translation: 一种淋浴头结构，包括主体，前壳体，按钮，导水构件，流量开关盘，第一出水口面板，第二出水口面板和第三出水口面板。 因此，用户只能用一只手来操作按钮，以便切换和调节水流，从而便于用户切换和调节淋浴头的水流。 此外，用户可以按压按钮来切换和调节通过第一出水口面板，第二出水口面板和第三出水口面板的水流，从而增强淋浴喷头的通用性。

公开(公告)号：USD470568S1

公开(公告)日：2003-02-18

申请号：US29160499

申请日：2002-05-14

Applicant: James Wu

Designer： James Wu

公开(公告)号：US06228736B1

公开(公告)日：2001-05-08

申请号：US09131117

申请日：1998-08-07

Applicant: Yu-Hua Lee ,  James Wu

Inventor： Yu-Hua Lee ,  James Wu

IPC: H01L2120

CPC classification number: H01L27/10855 ,  H01L28/91

Abstract: A modified method for forming cylinder-shaped stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas. A silicon nitride (Si3N4) etch-stop layer is deposited and first openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings. A Si3N4 second etch-stop layer is deposited and etched back to form protective sidewall spacers in the first openings when the polysilicon node contact is inadvertently overetched. A second SiO2 insulating layer is deposited and second openings for bottom electrodes are etched over the node contacts. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the first etch-stop layer. When the second openings are misaligned over the node contact openings, the Si3N4 sidewall spacers protect the SiO2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种用于形成用于DRAM的圆柱形叠层电容器的修改方法，其规避了由于未对准引起的氧化物侵蚀。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 沉积氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点触点的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 当多晶硅节点接触不经意地过蚀刻时，沉积并蚀刻Si 3 N 4第二蚀刻停止层以在第一开口中形成保护性侧壁间隔物。 沉积第二SiO 2绝缘层，并且在节点触点上蚀刻用于底部电极的第二开口。 沉积保形第二多晶硅层并在第二开口中化学/机械抛光以形成底部电极。 通过湿蚀刻将第二绝缘层去除到第一蚀刻停止层。 当第二开口在节点接触开口上不对准时，Si 3 N 4侧壁间隔物保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 现在通过在底部电极上形成电极间电介质层来完成电容器，并且沉积并构图用于顶部电极的第三多晶硅层。

公开(公告)号：US6027969A

公开(公告)日：2000-02-22

申请号：US090497

申请日：1998-06-04

Applicant: Kuo Ching Huang ,  James Wu

Inventor： Kuo Ching Huang ,  James Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Abstract translation: 已经开发了用于增加DRAM层叠电容器结构的表面积以及因此增加电容的方法。 通过使用多个多晶硅和绝缘体沉积，以及通过使用干各向异性和湿各向同性的蚀刻工艺，创建了包含多晶硅分支的存储节点电极。 在硅氧化物台面的侧面产生的多晶硅间隔物的使用增加了多晶硅分支的垂直分量。 从多晶硅分支之间去除绝缘体层的一部分导致增加的存储节点电极表面积的暴露。 在多晶硅分支之间的绝缘体层的未蚀刻部分为存储节点电极提供由多晶硅分支组成的结构支撑。