公开(公告)号：US09166580B2

公开(公告)日：2015-10-20

申请号：US14250487

申请日：2014-04-11

Applicant: Japan Display Inc.

Inventor： Motoharu Miyamoto ,  Takahiro Ochiai ,  Hideo Sato

IPC: H03K17/16

CPC classification number: H03K17/162 ,  H03K17/16

Abstract: A gate signal line drive circuit and a display using the circuit, which suppress a leak current to reduce a power consumption. A gate signal line drive circuit that supplies a high voltage in a signal high period, and supplies a low voltage in a signal low period, the gate signal line drive circuit including: a high voltage supply switching element that turns on in response to the high period, supplies a voltage of a first basic clock signal to gate signal lines; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines in response to the signal low period.

Abstract translation: 门信号线驱动电路和使用该电路的显示器，其抑制泄漏电流以降低功耗。 一种栅极信号线驱动电路，其在信号高周期中提供高电压，并且在信号低电平周期中提供低电压，所述栅极信号线驱动电路包括：高电压电源开关元件，其响应于高电平而导通 向栅极信号线提供第一基本时钟信号的电压; 高压电源断开控制电路，其响应于所述信号低周期而向所述高压电源开关元件的开关提供第一低电压; 以及低电压电源开关电路，其响应于所述信号低周期而将高于所述第一低电压的第二低电压提供给所述栅极信号线。

公开(公告)号：US09104077B2

公开(公告)日：2015-08-11

申请号：US14168062

申请日：2014-01-30

Applicant: Japan Display Inc.

Inventor： Takahiro Ochiai ,  Motoharu Miyamoto ,  Masahiro Hoshiba

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/136209 ,  G02F1/133512 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/1368 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2310/0202 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/78609 ,  H01L29/78633 ,  H01L29/78669

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract translation: 液晶显示装置设置有薄膜晶体管，该薄膜晶体管包括设置在位于第一绝缘层上的第一电极层中的栅极电极膜，经由第二绝缘层设置在栅电极膜上的半导体膜， 漏电极和源极，设置在位于所述半导体膜上方并与所述半导体膜的上表面接触的第二电极层中，以及设置在所述第一绝缘层下方的遮光膜。 其至少一部分在平面图中与半导体膜和栅电极膜重叠。 漏电极和源电极之一连接到栅极线，并且遮光膜与源电极电连接。

公开(公告)号：US09076403B2

公开(公告)日：2015-07-07

申请号：US14449363

申请日：2014-08-01

Applicant: Japan Display Inc. ,  Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroko Sehata ,  Hiroyuki Higashijima

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0465 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract translation: 一种包括双向移位寄存器电路的显示装置，包括：多个级联连接的寄存器电路; 各种电路，用于响应于输入到各种终端的各种信号将各种节点设置到各种电压电平; 以及输出电路，其在第一节点的电压为高电平时输出时钟脉冲作为输出脉冲，其中，在正向移位操作时，底部伪寄存器电路未输入复位信号和底部的第一节点 如果底部伪寄存器电路的初始复位电路接收到反向触发信号，则虚拟寄存器电路被复位，并且其中，在反向移位操作时，顶部伪寄存器电路不输入复位信号和顶部伪器件的第一个节点 如果顶部伪寄存器电路的初始复位电路接收到正向触发信号，则寄存器电路复位。