公开(公告)号：US07865700B2

公开(公告)日：2011-01-04

申请号：US12033052

申请日：2008-02-19

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/30

CPC分类号： G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3889

摘要： The present invention provides a system and method for prioritizing store instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: (1) receive an issue group of instructions; (2) determine if at least one store instruction is in the issue group, if so scheduling the least one store instruction in a one of the plurality of execution pipelines based upon a first prioritization scheme; (3) determine if there is an issue conflict for one of the plurality of execution pipelines and resolving the issue conflict by scheduling the at least one store instruction in a different execution pipeline; (4) schedule execution of the issue group of instructions in the cascaded delayed execution pipeline unit.

摘要翻译： 本发明提供了一种用于在级联管道中优先存储指令的系统和方法。 该系统包括具有多个执行流水线的级联延迟执行流水线单元，该多个执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。 该系统还包括被配置为：（1）接收问题组指令的电路; （2）确定在所述问题组中是否存在至少一个存储指令，如果是，则基于第一优先化方案在所述多个执行流水线中的一个中调度所述至少一个存储指令; （3）确定所述多个执行流水线之一是否存在问题冲突，并且通过在不同的执行流水线中调度所述至少一个存储指令来解决所述问题冲突; （4）调度级联延迟执行流水线单元中的问题组指令的执行。

公开(公告)号：US07594078B2

公开(公告)日：2009-09-22

申请号：US11351239

申请日：2006-02-09

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/30

CPC分类号： G06F12/0862 ,  G06F12/0855 ,  G06F12/0897 ,  G06F2212/6024 ,  G06F2212/6028

摘要： A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

摘要翻译： 提供了一种用于D-缓存未命中预测和调度的方法和装置。 在一个实施例中，调度处理器中的指令的执行。 处理器可以具有至少一个具有两个或更多个执行流水线的级联延迟执行流水线单元，该执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。 所述方法包括：接收问题组指令，确定所述问题组中的第一指令是否在先前执行所述第一指令期间导致高速缓存未命中，如果是，则在其中执行的流水线中调度要执行的所述第一指令 相对于级联延迟执行流水线单元中的另一流水线延迟。

公开(公告)号：US20090210666A1

公开(公告)日：2009-08-20

申请号：US12033043

申请日：2008-02-19

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/312

CPC分类号： G06F9/3853 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3889

摘要： The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: receive an issue group of instructions; determine if at least one load instruction is in the issue group, if so scheduling the least one load instruction in a one of the plurality of execution pipelines based upon a first prioritization scheme; determine if there is a issue conflict for one of the plurality of execution pipelines and resolving the issue conflict by scheduling the at least one load instruction in a different execution pipeline; and schedule execution of the issue group of instructions in the cascaded delayed execution pipeline unit.

摘要翻译： 本发明提供了用于级联管道的组优先级问题模式的系统和方法。 该系统包括具有多个执行流水线的级联延迟执行流水线单元，该多个执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。 所述系统还包括被配置为：接收问题组指令的电路; 确定所述问题组中是否存在至少一个加载指令，如果是，则基于第一优先级排列方案来调度所述多条执行流水线中的一条执行管道中的至少一条加载指令; 确定所述多个执行流水线之一是否存在问题冲突，并且通过在不同的执行管线中调度所述至少一个加载指令来解决所述问题冲突; 并且调度级联延迟执行流水线单元中的问题组指令的执行。

公开(公告)号：US20090210625A1

公开(公告)日：2009-08-20

申请号：US12030965

申请日：2008-02-14

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F12/10 ,  G06F12/08

CPC分类号： G06F12/1054 ,  G06F12/0862 ,  G06F12/0897

摘要： Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the LLB, thereby allowing access to the cache before the complete address translation is available and reducing cache access latency.

摘要翻译： 本发明的实施例提供了配置为将实际地址的一部分保留在翻译后备（TLB）缓冲器中以允许来自高速缓存的数据预取的查看备用缓冲器（LLB）。 可以从LLB相对快速地检索与有效地址相关联的真实地址位的子集，由此允许在完成地址转换可用之前访问高速缓存，并减少高速缓存访​​问等待时间。

公开(公告)号：US20090204792A1

公开(公告)日：2009-08-13

申请号：US12030252

申请日：2008-02-13

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/312

CPC分类号： G06F9/382 ,  G06F9/3822 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3889 ,  G06F9/3891

摘要： Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times. Separate processor cores may be morphed to appear differently for different applications. For example, two processor cores each capable of executing N-wide issue groups of instructions may be morphed to appear as a single processor core capable of executing 2N-wide issue groups.

摘要翻译： 提供了用于以流水线方式执行指令的改进技术，其可以减少执行依赖指令时发生的停顿。 可以通过利用具有相对于彼此延迟的执行单元的管道的级联排列来减少停顿。 这种级联延迟安排允许在普通问题组中发布相关指令，方法是调度它们以在不同管道中执行以在不同时间执行。 单独的处理器核心可能会变形为不同的应用程序显示不同。 例如，每个能够执行N个宽度的指令组的两个处理器核心可以被变形为能够执行2N个宽度的问题组的单个处理器核心。

公开(公告)号：US20080276075A1

公开(公告)日：2008-11-06

申请号：US12174538

申请日：2008-07-16

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/312

CPC分类号： G06F9/3853 ,  G06F9/30185 ,  G06F9/382 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3889 ,  G06F12/0859 ,  G06F2212/1008

摘要： Embodiments of the invention provide a method and processor for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction to be executed in the processor and detecting a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The method further includes scheduling execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.

摘要翻译： 本发明的实施例提供了一种用于执行指令的方法和处理器。 在一个实施例中，该方法包括接收要在处理器中执行的加载指令和存储指令，并检测加载指令与存储指令之间的冲突。 检测冲突包括确定加载存储冲突信息是否指示加载指令先前与存储指令冲突。 存储加载指令和存储指令的加载存储冲突信息。 该方法还包括调度加载指令和存储指令的执行，使得加载指令和存储指令的执行不会导致冲突。

公开(公告)号：US07447879B2

公开(公告)日：2008-11-04

申请号：US11351247

申请日：2006-02-09

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/3812 ,  G06F9/382 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3889

摘要： A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

摘要翻译： 提供了一种用于最小化非计划D缓存未命中管道失速的方法和装置。 在一个实施例中，调度处理器中的指令的执行。 处理器可以具有至少一个具有两个或更多个执行流水线的级联延迟执行流水线单元，该执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。 该方法包括接收问题组指令，确定发布组中的第一指令是否是加载指令，如果是，则在相对于另一流水线执行不延迟的流水线中调度要执行的第一指令 级联延迟执行流水线单元。

公开(公告)号：US20080162895A1

公开(公告)日：2008-07-03

申请号：US12048016

申请日：2008-03-13

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F9/30

CPC分类号： G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3889

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for minimizing unscheduled D-cache miss pipeline stalls is provided. The design structure includes an integrated circuit device, which includes a cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other, and circuitry. The circuitry is configured to receive an issue group of instructions, determine whether the issue group is a load instruction, and if so, schedule the load instruction in a first pipeline of the two or more execution pipelines, and schedule each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the first pipeline begins prior to beginning execution of the remaining instructions in the remaining pipelines.

摘要翻译： 提供了一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试用于最小化非预定D缓存未命中流水线失速的设计。 该设计结构包括集成电路设备，其包括具有两个或更多个执行流水线的级联延迟执行流水线单元，该执行流水线以相对于彼此的延迟方式开始执行共同问题组中的指令，以及电路。 电路被配置为接收问题组指令，确定问题组是否是加载指令，如果是，则在两个或更多个执行流水线的第一管道中调度加载指令，并且调度问题中的每个剩余指令 组在两条或更多条管道的剩余管线中执行，其中第一管道中的加载指令的执行在剩余管线中剩余指令开始执行之前开始。

公开(公告)号：US20070288734A1

公开(公告)日：2007-12-13

申请号：US11422930

申请日：2006-06-08

申请人： David A. Luick

发明人： David A. Luick

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30021 ,  G06F9/30101 ,  G06F9/3804 ,  G06F9/3812 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3846 ,  G06F9/3848 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3889 ,  G06F12/0862 ,  Y02D10/13

摘要： A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, issuing instructions for a first path of the branch instruction to a first queue of a dual instruction queue, and issuing instructions for a second path of the branch instruction to a second queue of a dual instruction queue. The method further includes determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the instructions for the first path are provided from the first queue are provided to a first execution unit. Upon determining that the branch instruction follows the second path, instructions for the second path are provided from the second queue to the first execution unit.

摘要翻译： 提供一种用于执行分支指令的方法和装置。 在一个实施例中，该方法包括：接收分支指令，将分支指令的第一路径的指令发送到双指令队列的第一队列，以及将分支指令的第二路径的指令发布到双重指令队列的第二队列 指令队列 该方法还包括确定分支指令是否遵循第一路径或第二路径。 在确定分支指令遵循第一路径时，从第一队列提供的第一路径的指令被提供给第一执行单元。 在确定分支指令遵循第二路径之后，第二路径的指令从第二队列提供给第一执行单元。

公开(公告)号：US20070288731A1

公开(公告)日：2007-12-13

申请号：US11422905

申请日：2006-06-08

申请人： Jeffrey P. Bradford ,  David A. Luick

发明人： Jeffrey P. Bradford ,  David A. Luick

IPC分类号： G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/30072 ,  G06F9/382 ,  G06F9/3828 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3869 ,  G06F9/3889

摘要： A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction and issuing one or more instructions from a first path of the branch instruction and one or more instructions from a second path of the branch instruction. If the first path of the branch instruction is followed by the branch instruction, the one or more instructions from the second path of the branch instruction are invalidated. If the second path of the branch instruction is followed by the branch instruction, the one or more instructions from the first path of the branch instruction are invalidated.

摘要翻译： 提供一种用于执行分支指令的方法和装置。 在一个实施例中，该方法包括从分支指令的第一路径接收分支指令和发出一个或多个指令以及来自分支指令的第二路径的一个或多个指令。 如果分支指令的第一路径跟随分支指令，则来自分支指令的第二路径的一个或多个指令无效。 如果分支指令的第二路径后面是分支指令，则来自分支指令的第一路径的一个或多个指令无效。