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公开(公告)号：US20120256242A1
公开(公告)日：2012-10-11
申请号：US13080390
申请日：2011-04-05
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译： 提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线 绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。
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公开(公告)号：US20110133161A1
公开(公告)日：2011-06-09
申请号：US12630939
申请日：2009-12-04
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。
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公开(公告)号：US08809131B2
公开(公告)日：2014-08-19
申请号：US13550861
申请日：2012-07-17
IPC分类号： H01L21/335
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.
摘要翻译： 一方面，制造纳米线FET器件的方法包括以下步骤。 提供晶片。 在堆叠中的晶片上形成至少一个牺牲层和硅层。 翅片在堆叠中被图案化。 虚拟门形成在将用作沟道区域的鳍的部分上，并且其中保持暴露的鳍的一个或多个部分将用作源极和漏极区。 围绕虚拟栅极沉积间隙填充材料并进行平面化处理。 移除在间隙填充材料中形成凹槽的伪栅极。 硅层（其将用作纳米线通道）的部分从沟槽内的翅片释放。 替代栅极形成在围绕纳米线通道的沟槽内的沟槽中，全部配置。 还提供了纳米线FET器件。
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公开(公告)号：US20140021538A1
公开(公告)日：2014-01-23
申请号：US13550861
申请日：2012-07-17
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.
摘要翻译： 一方面，制造纳米线FET器件的方法包括以下步骤。 提供晶片。 在堆叠中的晶片上形成至少一个牺牲层和硅层。 翅片在堆叠中被图案化。 虚拟门形成在将用作沟道区域的鳍的部分上，并且其中保持暴露的鳍的一个或多个部分将用作源极和漏极区。 围绕虚拟栅极沉积间隙填充材料并进行平面化处理。 移除在间隙填充材料中形成凹槽的伪栅极。 硅层（其将用作纳米线通道）的部分从沟槽内的翅片释放。 替代栅极形成在围绕纳米线通道的沟槽内的沟槽中，全部配置。 还提供了纳米线FET器件。
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65.发明申请Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers 有权无衬底栅极 - 全周围半导体纳米线FET在散装半导体晶片上公开(公告)号：US20130221328A1
公开(公告)日：2013-08-29
申请号：US13405732
申请日：2012-02-27
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/762
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译： 一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层 的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。
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公开(公告)号：US08507892B2
公开(公告)日：2013-08-13
申请号：US13372714
申请日：2012-02-14
IPC分类号： H01L29/66
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。
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公开(公告)号：US20120138900A1
公开(公告)日：2012-06-07
申请号：US13372714
申请日：2012-02-14
IPC分类号： H01L29/66
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。
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公开(公告)号：US08173993B2
公开(公告)日：2012-05-08
申请号：US12630942
申请日：2009-12-04
IPC分类号： H01L29/12
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管（FET）器件的方法包括：在半导体衬底上形成由第一和第二衬垫区域悬挂的纳米线，纳米线包括芯部分和电介质层，在该部分的一部分周围形成栅极结构 电介质层，在从所述栅极结构延伸的所述纳米线的一部分周围形成第一间隔物，在所述纳米线的第一部分中注入离子，将所述离子注入到所述纳米线的第二部分的介电层中，从所述第二部分去除所述电介质层 去除所述暴露的纳米线的第二部分的核心部分以形成空腔，并且从所述纳米线和所述第二焊盘区域的暴露的横截面外延生长所述空腔中的掺杂半导体材料，以将所述暴露的横截面 纳米线到第二垫区域。
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公开(公告)号：US20170194509A1
公开(公告)日：2017-07-06
申请号：US15180314
申请日：2016-06-13
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L29/0673 , H01L29/165 , H01L29/401 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/775 , H01L29/78618
摘要： A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.
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公开(公告)号：US08853790B2
公开(公告)日：2014-10-07
申请号：US13080390
申请日：2011-04-05
IPC分类号： H01L51/48 , H01L29/786 , H01L27/12 , H01L29/06 , B82Y10/00 , H01L29/423 , H01L21/84
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译： 提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线 绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。
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