公开(公告)号：US5753952A

公开(公告)日：1998-05-19

申请号：US532061

申请日：1995-09-22

申请人： Freidoon Mehrad

发明人： Freidoon Mehrad

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages V.sub.T, and improves device life because fewer electrons travel through the gate oxide (30).

摘要翻译： 集成电路存储单元（10）形成有PN结多晶浮动栅极（13），其中掺杂有源极（13B）的轻硼和在漏极侧（13A）上掺杂的重砷或磷加上沟道区 （Ch）。 电池（10）在半导体本体（22）的表面上以阵列形式形成，每个电池单元包括源（11）并包括漏极（12）。 通过在浮动栅极（13）中形成P-N结（JU）来实现改进的过擦除特性。 在多晶浮动栅极（13）中使用PN结（JU）可防止电池（10）耗尽，导致擦除的阈值电压VT的分布更严格，并且由于较少的电子通过栅极氧化物（30 ）。

公开(公告)号：US08372703B2

公开(公告)日：2013-02-12

申请号：US12908140

申请日：2010-10-20

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US07960280B2

公开(公告)日：2011-06-14

申请号：US11844832

申请日：2007-08-24

申请人： Freidoon Mehrad ,  Frank S. Johnson

发明人： Freidoon Mehrad ,  Frank S. Johnson

IPC分类号： H01L21/44

CPC分类号： H01L21/823835

摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices.

摘要翻译： 公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。 在一个示例中，该方法包括在PMOS器件的栅电极的至少顶部部分中形成第一硅化物，而不是在NMOS器件上形成。 该方法还包括在NMOS和PMOS器件的栅电极的至少顶部中同时形成第二硅化物，以及形成栅电极的FUSI栅极硅化物。 在一个实施例中，第二硅化物的厚度大于第一硅化物的量，该量补偿了NMOS和PMOS器件之间的硅化物形成速率的差异。

公开(公告)号：US07943456B2

公开(公告)日：2011-05-17

申请号：US12347173

申请日：2008-12-31

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Brian K. Kirkpatrick

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Brian K. Kirkpatrick

IPC分类号： H01L21/8238 ,  H01L29/80

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）和其IC的方法包括提供具有包括用于PMOS器件的PMOS区域和NMOS器件的NMOS区域的半导体表面的衬底。 包括栅极电极层的栅极堆叠形成在PMOS区域和NMOS区域中的栅极电介质层中或栅极电介质层上。 使用n型掺杂来在PMOS和NMOS区域中的栅极堆叠的相对侧上产生n型湿法蚀刻增感区域。 湿式蚀刻去除在（i）所述PMOS区域的至少一部分中的n型湿法蚀刻增感区域以形成多个PMOS源极/漏极凹槽，或（ii）在所述NMOS区域的至少一部分中形成多个 的NMOS源/漏极凹槽，或（i）和（ii）。 至少一个压应变诱导外延层形成在多个PMOS源极/漏极凹槽中，并且在多个NMOS源极/漏极凹槽中形成拉伸应变诱发外延层。 然后完成IC的制造。

公开(公告)号：US07910422B2

公开(公告)日：2011-03-22

申请号：US12241798

申请日：2008-09-30

申请人： Freidoon Mehrad ,  Jinhan Choi ,  Frank Scott Johnson

发明人： Freidoon Mehrad ,  Jinhan Choi ,  Frank Scott Johnson

IPC分类号： H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823842

摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

摘要翻译： 公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。 该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。 该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层 。 该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

公开(公告)号：US07892906B2

公开(公告)日：2011-02-22

申请号：US12022488

申请日：2008-01-30

申请人： Freidoon Mehrad ,  Frank S. Johnson

发明人： Freidoon Mehrad ,  Frank S. Johnson

IPC分类号： H01L21/8234

CPC分类号： H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A layer of silicidation metal is formed and a first silicide anneal changes the undoped polysilicon gate electrodes into partially silicided gate electrodes. Dopants of a first type and a second type are implanted into the partially silicided gate electrode of the PMOS and NMOS transistors and a second silicide anneal is performed to change the doped partially silicided gate electrodes into fully silicided gate electrodes.

摘要翻译： 一种制造CMOS晶体管的方法，包括形成NMOS晶体管和具有未掺杂多晶硅栅电极和硬掩模的PMOS晶体管。 该方法还包括形成绝缘材料层，然后去除硬掩模和绝缘材料层的一部分。 形成硅化金属层，并且第一硅化物退火将未掺杂的多晶硅栅电极改变成部分硅化栅电极。 将第一类型和第二类型的掺杂剂注入到PMOS和NMOS晶体管的部分硅化物栅电极中，并且执行第二硅化物退火以将掺杂的部分硅化栅电极改变为完全硅化的栅电极。

公开(公告)号：US07763540B2

公开(公告)日：2010-07-27

申请号：US11741064

申请日：2007-04-27

申请人： Frank Scott Johnson ,  Freidoon Mehrad

发明人： Frank Scott Johnson ,  Freidoon Mehrad

IPC分类号： H01L21/44

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/66545

摘要： A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.

摘要翻译： 一种用于制造半导体器件的方法包括利用CMP叠层形成硅化栅。 CMP堆叠包括形成在下面的半导体器件上的第一衬垫和形成在第一衬里层上的第一介电层。 第一电介质层形成为大约高度的栅极。 在第一介电层上形成第二衬里层。 由于第一电介质层形成为大致高度的栅极，护套区域上的第二衬垫大约在栅极上的第一衬垫的高度处。 执行CMP处理以在栅极的顶部上露出第一衬垫。 由于第一电介质层形成到栅极的高度，所以在CMP工艺之后，第二衬里的一部分保留在护环区域之上。 之后，露出栅极，进行硅化处理以形成硅化栅极。

公开(公告)号：US20100164008A1

公开(公告)日：2010-07-01

申请号：US12647074

申请日：2009-12-24

申请人： Freidoon Mehrad ,  James J. Chambers ,  Shaofeng Yu

发明人： Freidoon Mehrad ,  James J. Chambers ,  Shaofeng Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/66545 ,  H01L29/6659

摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.

摘要翻译： 提供半导体器件和制造方法，其中为CMOS晶体管提供金属晶体管替代栅极。 该过程在CMOS工艺中提供双重或差分工作功能能力（例如，用于PMOS和NMOS晶体管）。

公开(公告)号：US07585738B2

公开(公告)日：2009-09-08

申请号：US11741540

申请日：2007-04-27

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

公开(公告)号：US20090057776A1

公开(公告)日：2009-03-05

申请号：US11741551

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Craig H. Huffman

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Craig H. Huffman

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.

摘要翻译： 一种形成具有独立多晶硅栅极厚度的完全硅化的NMOS和PMOS半导体器件的方法及相关器件。 至少一些说明性实施例是包括在半导体衬底（具有第一厚度的N型栅极）上形成N型栅极的方法，在半导体衬底上形成P型栅极（P型栅极具有 第二厚度不同于第一厚度），并且执行N型栅极和P型栅极的同时硅化。