公开(公告)号：US07902035B2

公开(公告)日：2011-03-08

申请号：US12484911

申请日：2009-06-15

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L21/76

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US07745890B2

公开(公告)日：2010-06-29

申请号：US11863804

申请日：2007-09-28

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US07612405B2

公开(公告)日：2009-11-03

申请号：US11714644

申请日：2007-03-06

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

摘要翻译： 半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。 第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。 第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。 第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同 厚度

公开(公告)号：US20090096002A1

公开(公告)日：2009-04-16

申请号：US11872546

申请日：2007-10-15

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L2029/7858

摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。

公开(公告)号：US20080265338A1

公开(公告)日：2008-10-30

申请号：US11741580

申请日：2007-04-27

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US20080265321A1

公开(公告)日：2008-10-30

申请号：US11741602

申请日：2007-04-27

申请人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.

摘要翻译： 提供了具有改善的源极/漏极区域的鳍状场效应晶体管（finFET）。 在一个实施例中，去除鳍片的源极/漏极区域，同时留下与鳍片相邻的间隔物。 倾斜的注入用于在栅电极附近注入源极/漏极区，从而允许更均匀的轻掺杂漏极。 鳍可以通过外延生长或金属化过程重新形成。 在另一个实施例中，去除与源极/漏极区域中的鳍片相邻的间隔物，并且翅片沿翅片的侧面和顶部被硅化。 在另一个实施例中，在源极/漏极区域中去除鳍片和间隔物。 然后通过外延生长工艺或金属化工艺重新形成翅片。 也可以使用这些实施例的组合。

公开(公告)号：US20080197420A1

公开(公告)日：2008-08-21

申请号：US11707490

申请日：2007-02-16

申请人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

发明人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

摘要翻译： 一种制造双栅极半导体器件的方法。 优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料， 蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。 然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。 在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

公开(公告)号：US07094683B2

公开(公告)日：2006-08-22

申请号：US10633909

申请日：2003-08-04

申请人： Chen-Nan Yeh ,  Yung-Cheng Lu

发明人： Chen-Nan Yeh ,  Yung-Cheng Lu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76804

摘要： A method for forming a dual damascene opening to protect a low-K dielectric insulating layer including providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack layer comprising at least one dielectric insulating layer over the at least one dielectric insulating to seal the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; photolithographically patterning and etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; and, etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.

摘要翻译： 一种用于形成双镶嵌开口以保护低K介电绝缘层的方法，包括提供半导体工艺晶片，其包括通过至少一个介电绝缘层的厚度部分延伸的通孔; 在所述至少一个电介质绝缘体上沉积包括至少一个介电绝缘层的第一介电层堆叠层，以密封所述通孔开口; 包覆沉积包括至少一个电介质层的第二介电层堆叠，以在第一介电层堆叠之上形成硬掩模，并与第一介电层堆叠接触; 通过硬掩模和第一介电层堆叠的厚度进行光刻图案化和蚀刻，以形成覆盖并包围通孔孔的沟槽开口蚀刻图案，同时使通孔开口密封; 并且蚀刻穿过所述至少一个介电绝缘层的厚度部分以形成双镶嵌开口。