公开(公告)号：US07510940B2

公开(公告)日：2009-03-31

申请号：US11707490

申请日：2007-02-16

申请人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

发明人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

摘要翻译： 一种制造双栅极半导体器件的方法。 优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料， 蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。 然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。 在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

公开(公告)号：US20080197420A1

公开(公告)日：2008-08-21

申请号：US11707490

申请日：2007-02-16

申请人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

发明人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

摘要翻译： 一种制造双栅极半导体器件的方法。 优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料， 蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。 然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。 在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

公开(公告)号：US07109085B2

公开(公告)日：2006-09-19

申请号：US11033912

申请日：2005-01-11

申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US06900104B1

公开(公告)日：2005-05-31

申请号：US10788754

申请日：2004-02-27

申请人： Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Yuan-Hung Chiu

发明人： Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Yuan-Hung Chiu

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823864 ,  H01L29/6659

摘要： A method for forming an offset spacer adjacent a CMOS gate structure with improved critical dimension control including providing a substrate that has a gate structure; forming at least one oxide layer over the substrate; forming at least one nitride layer over the at least one oxide layer; dry etching the at least one nitride layer in a first dry etching process to expose a first portion of the at least one oxide layer; carrying out a wet etching process to remove the first portion of the at least one oxide layer; and, dry etching the at least one nitride layer in a second dry etching process to remove the at least one nitride layer leaving a second portion of the at least one oxide layer to form an oxide offset spacer along sidewalls of the gate structure.

摘要翻译： 一种用于在具有改进的临界尺寸控制的CMOS栅极结构附近形成偏移间隔物的方法，包括提供具有栅极结构的衬底; 在衬底上形成至少一个氧化物层; 在所述至少一个氧化物层上形成至少一个氮化物层; 在第一干蚀刻工艺中干蚀刻所述至少一个氮化物层以暴露所述至少一个氧化物层的第一部分; 执行湿蚀刻工艺以去除所述至少一个氧化物层的第一部分; 并且在第二干蚀刻工艺中干蚀刻所述至少一个氮化物层以移除所述至少一个氮化物层，留下所述至少一个氧化物层的第二部分，以在所述栅极结构的侧壁上形成氧化物偏置间隔物。

公开(公告)号：US20060154487A1

公开(公告)日：2006-07-13

申请号：US11033912

申请日：2005-01-11

申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/8234 ,  H01L21/302

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US20050032386A1

公开(公告)日：2005-02-10

申请号：US10634001

申请日：2003-08-04

申请人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

发明人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/32137

摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.

摘要翻译： 一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅 蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

公开(公告)号：US08236659B2

公开(公告)日：2012-08-07

申请号：US12816519

申请日：2010-06-16

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US07301645B2

公开(公告)日：2007-11-27

申请号：US11053300

申请日：2005-02-07

申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

IPC分类号： G01B11/02

CPC分类号： H01L22/20

摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

公开(公告)号：US07012027B2

公开(公告)日：2006-03-14

申请号：US10766596

申请日：2004-01-27

申请人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

发明人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

摘要： A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

摘要翻译： 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。