公开(公告)号：US20100221878A1

公开(公告)日：2010-09-02

申请号：US12777937

申请日：2010-05-11

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20090085126A1

公开(公告)日：2009-04-02

申请号：US11863804

申请日：2007-09-28

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC分类号： H01L29/00

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 半导体系统包括PMOS栅极结构，PMOS栅极结构包括第一高k电介质层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高k电介质 层，P金属层和形成在P金属层上的完全硅化物层。 半导体系统还包括NMOS栅极结构，NMOS栅极结构包括第二高k电介质层，完全硅化层和中间间隙金属层，其中中间间隙金属层形成在高kappa 电介质和完全硅化物层。

公开(公告)号：US07745890B2

公开(公告)日：2010-06-29

申请号：US11863804

申请日：2007-09-28

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US07977772B2

公开(公告)日：2011-07-12

申请号：US12777937

申请日：2010-05-11

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC分类号： H01L21/4763

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20080230844A1

公开(公告)日：2008-09-25

申请号：US11688592

申请日：2007-03-20

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

摘要： A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

摘要翻译： 提供了一种用于形成具有减小的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

公开(公告)号：US07629655B2

公开(公告)日：2009-12-08

申请号：US11688592

申请日：2007-03-20

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

摘要： A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

摘要翻译： 提供了一种用于形成具有降低的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

公开(公告)号：US09230959B2

公开(公告)日：2016-01-05

申请号：US13314942

申请日：2011-12-08

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

公开(公告)号：US20090095980A1

公开(公告)日：2009-04-16

申请号：US11873156

申请日：2007-10-16

申请人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

发明人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

IPC分类号： H01L29/778 ,  H01L29/786

CPC分类号： H01L29/1033 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

摘要翻译： 半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。 半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

公开(公告)号：US20090035909A1

公开(公告)日：2009-02-05

申请号：US11831098

申请日：2007-07-31

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu ,  Ding-Yuan Chen

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu ,  Ding-Yuan Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.

摘要翻译： 本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。 在第一散热片上形成第一层。 第一层包括第一类型的掺杂剂。 第二类型的掺杂剂被提供到第二鳍。 在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

公开(公告)号：US09048259B2

公开(公告)日：2015-06-02

申请号：US13562805

申请日：2012-07-31

申请人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

摘要翻译： 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。