公开(公告)号：US07061421B1

公开(公告)日：2006-06-13

申请号：US11096163

申请日：2005-03-31

申请人： Jinwen Xiao ,  Ka Y. Leung ,  Douglas R. Holberg

发明人： Jinwen Xiao ,  Ka Y. Leung ,  Douglas R. Holberg

IPC分类号： H03M1/78

CPC分类号： H03M1/363 ,  H02M3/33592 ,  Y02B70/1475

摘要： A differential analog-to-digital data converter (ADC) is disclosed for receiving a positive input signal and a negative input signal. A distributed resistive device is provided having taps associated therewith. A plurality of comparators each having a signal input and a reference input are provided, the signal input connected to one of the positive and negative input signals and the reference input connected to a tap on said distributed resistive device. A driver drives current through the distributed resistive device with one of the taps of the distributed resistive device disposed at substantially the other of the positive and negative input signals. A current varying device varys the current through the distributed resistive device to vary the voltage between taps.

摘要翻译： 公开了用于接收正输入信号和负输入信号的差分模数转换器（ADC）。 提供具有与其相关联的抽头的分布式电阻装置。 提供了各自具有信号输入和参考输入的多个比较器，所述信号输入连接到正输入信号和负输入信号中的一个以及连接到所述分布式电阻装置上的抽头的基准输入。 驱动器驱动电流通过分布式电阻器件，分布式电阻器件的抽头中的一个位于基本上正负输入信号的另一个处。 电流变化的装置通过分布式电阻装置改变电流以改变抽头之间的电压。

公开(公告)号：US07047263B2

公开(公告)日：2006-05-16

申请号：US09929855

申请日：2001-08-14

申请人： James L. Todsen ,  Ka Y. Leung ,  Timothy V. Kalthoff

发明人： James L. Todsen ,  Ka Y. Leung ,  Timothy V. Kalthoff

IPC分类号： G06F17/17 ,  G06F17/10

CPC分类号： H03H17/0283

摘要： A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected. For example, a filter path can be suitably configured with a multiplier component such that an equalized gain can be realized for each filter path. In addition, the various filters of the digital filter circuit can be configured within the parallel arrangement to provide reduce layout requirements through the sharing of components. For example, a second filter can share at least two integrators with the third filter, and the first filter can share at least one integrator with the third filter. Further, the digital filter can be suitably configured for operation in various industrial applications. For example, the first filter can be suitably configured with a notch filter configured to replace the first, third and other odd harmonic notches of the first filter.

摘要翻译： 提供了一种技术和电路，用于促进数字滤波器与模数转换器一起使用的更快的建立时间。 一种示例性技术利用复合滤波器用于具有较慢建立的较高噪声分辨率滤波器的并行配置的更快建立的较低噪声分辨率滤波器。 因此，可以更快地接收有效数据以供模拟数字转换器处理。 此外，复合数字滤波器电路可以包括三滤波器配置，其包括快速稳定，低分辨率第一滤波器，较慢稳定的，较高分辨率的第二滤波器，以及甚至更慢稳定，甚至更高分辨率的第三滤波器， 滤波器以并联的方式配置。 还可以提供额外的或更少的过滤器。 此外，每个滤波器路径的增益可以适当地匹配数字滤波器电路中的任何其它滤波器路径的增益，以提供具有均衡增益的滤波器输出，而不管所选择的滤波器路径如何。 例如，滤波器路径可以适当地配置有乘法器组件，使得可以为每个滤波器路径实现均衡的增益。 此外，数字滤波器电路的各种滤波器可以在并行布置内配置，以通过共享组件来提供降低的布局要求。 例如，第二滤波器可以与第三滤波器共享至少两个积分器，并且第一滤波器可以与第三滤波器共享至少一个积分器。 此外，数字滤波器可以适当地构造用于在各种工业应用中操作。 例如，第一滤波器可以适当地配置有陷波滤波器，该陷波滤波器被配置为代替第一滤波器的第一，第三和其它奇数谐波陷波。

公开(公告)号：US06950052B2

公开(公告)日：2005-09-27

申请号：US10735163

申请日：2003-12-12

申请人： Ka Y. Leung

发明人： Ka Y. Leung

IPC分类号： G06F13/28 ,  H01C10/16 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/38 ,  H03M1/46 ,  H03M1/66 ,  H03M1/78

CPC分类号： H03M1/1057 ,  H03M1/08 ,  H03M1/466 ,  H03M1/468

摘要： Noise cancellation in a single ended SAR converter. A single ended SAR converter front end is disclosed with common mode driver noise cancellation. The SAR converter front end includes a differential amplifier having positive and negative inputs and an output. A switched capacitor array is provided that is operable in a SAR data conversion operation to vary the voltage on one of the positive or negative inputs of the differential amplifier. A common mode driver drives a common mode node with a low impedance common mode voltage signal to a common mode node, and switching circuitry then switches the common mode voltage signal on the common mode node to the positive and negative inputs of the differential amplifier during a portion of a SAR data conversion cycle. A capacitor reference circuit is attached to the other of the positive or negative inputs of the differential, amplifier during at least the portion of the SAR data conversion cycle, the capacitor reference circuit and the capacitor array during at least the portion of the SAR data conversion cycle having relative capacitance values that increase the common mode rejection of any noise introduced to the common mode node at the input of the differential amplifier.

摘要翻译： 单端SAR转换器中的噪声消除。 公开具有共模驱动器噪声消除的单端SAR转换器前端。 SAR转换器前端包括一个具有正负输入和输出的差分放大器。 提供了开关电容器阵列，其可在SAR数据转换操作中操作以改变差分放大器的正或负输入之一上的电压。 共模驱动器将具有低阻抗共模电压信号的共模节点驱动到共模节点，并且开关电路然后将共模节点上的共模电压信号切换到差分放大器的正和负输入 部分SAR数据转换周期。 在SAR数据转换周期的至少部分，电容器参考电路和电容器阵列的至少部分SAR数据转换期间，电容器参考电路附加到差分放大器的正或负输入中的另一个 周期具有相对电容值，其增加在差分放大器的输入处引入到共模节点的任何噪声的共模抑制。

公开(公告)号：US06448916B1

公开(公告)日：2002-09-10

申请号：US09668871

申请日：2000-09-25

申请人： Ka Y. Leung

发明人： Ka Y. Leung

IPC分类号： H03M166

CPC分类号： H03M1/0663 ,  H03M1/682 ,  H03M1/765

摘要： In a segmented DAC having dual main DAC resistor strings and dual sub-DAC resistor strings, an interpolation circuit for averaging the selected voltage from each sub-DAC resistor string. A first switch multiplexer selects a voltage from the first sub-DAC resistor string, and a second switch multiplexer selects a similar voltage from a second sub-DAC resistor string. The selected analog voltages are coupled to high impedance inputs of a differential averaging circuit. An output voltage is fed back to the differential circuit. Once the differential averaging circuit settles, a quiescent feedback voltage exists which is exactly between the two analog voltages to be interpolated. The non-linearity of the DAC is substantially reduced.

摘要翻译： 在具有双主DAC电阻串和双子DAC电阻串的分段DAC中，用于对来自每个子DAC电阻串的选定电压进行平均的内插电路。 第一开关多路复用器选择来自第一子DAC电阻串的电压，第二开关多路复用器从第二子DAC电阻串中选择类似的电压。 选择的模拟电压耦合到差分平均电路的高阻抗输入端。 输出电压反馈到差分电路。 一旦差分平均电路稳定，就存在一个静态反馈电压，它恰好在要插补的两个模拟电压之间。 DAC的非线性大大降低。

公开(公告)号：US06433717B1

公开(公告)日：2002-08-13

申请号：US09584217

申请日：2000-05-31

申请人： Ka Y. Leung

发明人： Ka Y. Leung

IPC分类号： H03M166

CPC分类号： H03M1/0663 ,  H03M1/682 ,  H03M1/765

摘要： A digital-to-analog converter having a main DAC resistor string formed in a semiconductor material. The main DAC resistor string is formed as two identical resistor strings connected in parallel and such that the bottom of one resistor string and the top of the other resistor string are connected to a first voltage. The other ends of the resistor strings are coupled to a second different voltage. A switch multiplexer serving two functions is connected between the resistor strings. Each switch of the multiplexer interconnects similar voltage nodes of each resistor string together to thereby average the voltage should the resistance values differ due to semiconductor process variations. The switch multiplexer also serves to select one resistor of each resistor string to couple the voltage thereacross to a sub-resistor string of the digital-to-analog converter.

摘要翻译： 具有形成在半导体材料中的主DAC电阻串的数模转换器。 主DAC电阻串形成为并联连接的两个相同的电阻串，使得一个电阻串的底部和另一个电阻串的顶部连接到第一电压。 电阻串的另一端耦合到第二不同的电压。 两个功能的开关多路复用器连接在电阻串之间。 多路复用器的每个开关将每个电阻串的类似电压节点互连在一起，从而平均电压，如果电阻值由于半导体工艺变化而不同。 开关多路复用器还用于选择每个电阻器串的一个电阻器以将其上的电压耦合到数模转换器的子电阻器串。

公开(公告)号：US06384763B1

公开(公告)日：2002-05-07

申请号：US09583341

申请日：2000-05-31

申请人： Ka Y. Leung ,  Douglas R. Holberg

发明人： Ka Y. Leung ,  Douglas R. Holberg

IPC分类号： H03M178

CPC分类号： H03M1/0602 ,  H03M1/682 ,  H03M1/765

摘要： A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.

摘要翻译： 具有串联连接的晶体管的数模转换器形成用于各个分段电阻串的高阻抗电流源。 形成用于一个电阻器串的电流吸收器的串联晶体管通过利用负反馈放大器呈现高输出阻抗。 通过使用适当的增益电阻配置输出放大器，可以消除一个电阻串中的裕量电阻和偏移电阻的影响。 通过使用相同值的主电阻和子电阻串的所有电阻，可以实现高精度的D / A转换。

公开(公告)号：US06307497B1

公开(公告)日：2001-10-23

申请号：US09638095

申请日：2000-08-11

申请人： Ka Y. Leung ,  Douglas S. Piasecki

发明人： Ka Y. Leung ,  Douglas S. Piasecki

IPC分类号： H03M116

CPC分类号： H03M1/129 ,  H03M1/46

摘要： A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

摘要翻译： 用于模数转换器的可编程增益电路。 开关电容器网络将来自DAC的模拟基准电容耦合到比较器，使得可以将输入模拟信号的采样幅度与所述模拟参考值进行比较。 采样电容器的电容与开关电容网络的电容之比建立了要转换的模拟信号的有效增益。