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    CAPACATIVE ISOLATOR WITH SCHMITT TRIGGER
    2.
    发明申请
    CAPACATIVE ISOLATOR WITH SCHMITT TRIGGER 有权
    电容式隔离器与SCHMITT TRIGGER

    公开(公告)号：US20120161841A1

    公开(公告)日：2012-06-28

    申请号：US12976020

    申请日：2010-12-22

    申请人： Zhiwei Dong ,  Ka Y. Leung

    发明人： Zhiwei Dong ,  Ka Y. Leung

    IPC分类号： H03K3/00

    CPC分类号： H03K3/3565

    摘要： High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

    摘要翻译： 使用第一集成电路管芯提供高电压隔离能力，所述第一集成电路管芯包括反相电路路径和非反相电路路径，所述反相电路路径和非反相电路路径被耦合以接收单端信号并从单端信号产生差分信号以通过隔离传输 链接。 第二集成电路管芯包括与通过隔离链路传送的差分信号耦合的差分施密特触发器电路，并提供与其对应的至少一个输出信号。 隔离屏障设置在反相和非反相电路路径和差分施密特触发电路之间，并且包括耦合以分别传输差分信号的每个部分的至少两个隔离电容器。

    Method and apparatus for emulating rewritable memory with non-rewritable memory in an MCU
    4.
    发明授权
    Method and apparatus for emulating rewritable memory with non-rewritable memory in an MCU 有权
    用于在MCU中仿真具有不可重写存储器的可重写存储器的方法和装置

    公开(公告)号：US07680976B2

    公开(公告)日：2010-03-16

    申请号：US11695014

    申请日：2007-03-31

    申请人： Ka Y. Leung

    发明人： Ka Y. Leung

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0238 ,  G06F12/0246 ,  G06F2212/1056 ,  G06F2212/7202

    摘要： An integrated circuit having an embedded multiple time programmable memory includes a processing core for executing stored instructions with a data memory and a non volatile memory. The non-volatile memory block provides for storage of program instructions and includes a plurality of blocks of non-volatile memory, each of which can be written to once and read from many times and each having a size that is equal to or less than a program memory address space addressable by the processing core for output of data there from. It also includes a reserve storage location for storing a status word defining the one of the plurality of blocks addressable by the processing core, the status word operable to be changed in response to external signals when another of the plurality of blocks is to be selected, such that once another of the plurality of blocks is selected, the status word cannot indicate as addressable by the processing core a prior one of the plurality of blocks that was defined by the status word as being previously addressable by the processing core.

    摘要翻译： 具有嵌入式多时间可编程存储器的集成电路包括用于使用数据存储器和非易失性存储器执行存储的指令的处理核心。 非易失性存储器块提供程序指令的存储，并且包括多个非易失性存储器块，每个块可被写入一次并且从多次读取并且每个具有等于或小于 程序存储器地址空间可由处理核心寻址，用于输出数据。 它还包括一个保留存储位置，用于存储定义可由处理核心寻址的多个块中的一个的状态字，该状态字可操作以在多个块中的另一个块被选择时响应于外部信号被改变， 使得一旦选择了多个块中的另一个，则状态字不能被处理核心指示，该状态字由状态字定义为可由处理核心预先寻址的多个块中的先前的一个块。

    PID based controller for DC—DC converter with post-processing filters
    6.
    发明授权
    PID based controller for DC—DC converter with post-processing filters 失效
    基于PID的控制器，用于具有后处理滤波器的DC-DC转换器

    公开(公告)号：US07245512B2

    公开(公告)日：2007-07-17

    申请号：US11096598

    申请日：2005-03-31

    申请人： Ka Y. Leung ,  Kafai Leung ,  Jinwen Xiao

    发明人： Ka Y. Leung ,  Kafai Leung ,  Jinwen Xiao

    IPC分类号： H02M3/335

    CPC分类号： H02M3/3376 ,  H02M3/33561 ,  H02M3/33592 ,  H02M2001/0012 ,  Y02B70/1475

    摘要： A digital PID controller for controlling the operation of a switching power converter is disclosed. A data converter is provided for converting the analog sense voltage to a digital sense voltage. A difference circuit then determines the difference between the digital sense voltage and a reference voltage as a digital error voltage, which reference voltage represents a desired output DC voltage for the power converter. A digital compensator processes the digital error voltage. The digital compensator includes a PID compensation network for compensating the digital error signal with a discrete time PID control law and a postprocessing filter for processing the output of the PID compensation network, comprised of a sinc filter with variable parameters to define the operating characteristics thereof, such that a first notch associated therewith can be placed at a desired frequency. A switching control signal generator generates switching control signals for controlling the operation of the power converter, wherein the digital compensator and the switching control signal generator operate to minimize the digital error signal. A controller for controls the operation the digital compensator to define the operating characteristics of the sinc filter.

    摘要翻译： 公开了一种用于控制开关电源转换器的操作的数字PID控制器。 提供了一种数据转换器，用于将模拟检测电压转换为数字检测电压。 然后，差分电路将数字感测电压和参考电压之间的差作为数字误差电压确定，该参考电压表示功率转换器的期望的输出直流电压。 数字补偿器处理数字误差电压。 数字补偿器包括用于利用离散时间PID控制定律补偿数字误差信号的PID补偿网络和用于处理PID补偿网络的输出的后处理滤波器，其包括具有可变参数的sinc滤波器以限定其操作特性， 使得与其相关联的第一切口可以以期望的频率放置。 开关控制信号发生器产生用于控制功率转换器的操作的开关控制信号，其中数字补偿器和开关控制信号发生器操作以最小化数字误差信号。 控制器，用于控制数字补偿器的操作，以定义正弦滤波器的工作特性。

    DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU accesses memory
    7.
    发明授权
    DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU accesses memory 失效
    DMA控制器在CPU访问存储器时不会中断数字字的产生，从而限制ADC的内存

    公开(公告)号：US07188199B2

    公开(公告)日：2007-03-06

    申请号：US10752740

    申请日：2004-01-07

    申请人： Kafai Leung ,  Ka Y. Leung

    发明人： Kafai Leung ,  Ka Y. Leung

    IPC分类号： G06F3/00 ,  H03M1/12

    CPC分类号： H03M1/1057 ,  G06F13/28 ,  H03M1/468

    摘要： DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal and convert discrete samples thereof at a predetermined sampling rate to a digital representations thereof as a plurality of digital words. A memory stores the digital words generated by the data conversion circuit. A processor is included on the integrated circuit and operable to access the memory to output select ones of the digital words for processing thereof in accordance with a predetermined processing algorithm. A memory access controller controls access to the memory by the data conversion circuit and the processor. The memory access controller is operable to restrict access to the memory by the data conversion circuit without interrupting the generation of digital words therefrom when the processor is accessing the memory, and allowing access to the memory by the data conversion circuitry when the processor is not accessing the memory, such that the data conversion circuit can transfer currently generated digital words and previously generated and non stored digital words for storage in said memory upon gaining access thereto.

    摘要翻译： DMA控制器用于混合信号装置。 公开了一种具有存储器控制的混合信号集成电路。 提供了一种数据转换电路，其可操作以接收模拟输入信号并将其以预定采样率的离散采样转换为其数字表示作为多个数字字。 存储器存储由数据转换电路产生的数字字。 处理器被包括在集成电路中并且可操作以访问存储器以根据预定的处理算法输出用于处理的数字字的选择数字字。 存储器访问控制器通过数据转换电路和处理器控制对存储器的访问。 存储器访问控制器可操作以在处理器访问存储器时限制对数据转换电路对存储器的访问，而不会在处理器访问存储器时中断数字字的产生，并且当处理器未访问时允许数据转换电路访问存储器 存储器，使得数据转换电路可以传送当前生成的数字字和先前生成的和未存储的数字字，以便在访问存储器时存储在所述存储器中。

    Common centroid layout for parallel resistors in an amplifier with matched AC performance
    8.
    发明授权
    Common centroid layout for parallel resistors in an amplifier with matched AC performance 失效

    公开(公告)号：US06954167B2

    公开(公告)日：2005-10-11

    申请号：US10735387

    申请日：2003-12-12

    申请人： Ka Y. Leung

    发明人： Ka Y. Leung

    IPC分类号： G06F13/28 ,  H01C10/16 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/38 ,  H03M1/46 ,  H03M1/66 ,  H03M1/78

    CPC分类号： H03M1/1057 ,  H03M1/0648 ,  H03M1/466 ,  H03M1/468

    摘要： Common centroid layout for parallel resistors in an amplifier with matched AC performance. An amplifier is disclosed that is formed on a silicon substrate that includes first and second differential legs, each driving first and second resistive loads. The first resistive load comprises first and second parallel resistive loads connected on one side thereof to one end of the first differential leg and the other side of each of the first and second parallel resistive loads separately connected to a first reference voltage. The second resistive load comprises third and fourth resistive loads each connected on one side thereof to one end of the second differential leg and the other side of each of the third and fourth parallel resistive loads connected separately to the first reference voltage. Each of the first, second, third and fourth resistive loads is fabricated of a strip of resistive material disposed on the surface of the substrate and having a finite resistivity, length, width and thickness. The first parallel resistive load is disposed adjacent to a first dummy resistive strip on one side thereof, and disposed adjacent the third parallel resistive load on the opposite side thereof. The third parallel resistive load is disposed adjacent a second dummy resistive strip disposed on the diametrically opposite side thereof from the first parallel resistive load. The fourth parallel resistive load is disposed adjacent the second dummy resistive strip on the diametrically opposite side thereof from the third parallel resistive load. The second resistive load is disposed adjacent the fourth parallel resistive load and capacitively coupled thereto on the side diametrically opposite to the second dummy resistive strip. The second parallel resistive load is disposed adjacent a third dummy resistive strip on the side thereof diametrically opposite to the fourth parallel resistive load and capacitively coupled thereto. The first, second and third dummy resistive strips are connected to a second reference voltage.

    Mixed signal processor with noise management
    9.
    发明授权
    Mixed signal processor with noise management 有权
    具有噪声管理的混合信号处理器

    公开(公告)号：US06950044B1

    公开(公告)日：2005-09-27

    申请号：US10816262

    申请日：2004-03-31

    申请人： Douglas Piasecki ,  Ka Y. Leung

    发明人： Douglas Piasecki ,  Ka Y. Leung

    IPC分类号： H03M1/00 ,  H03M1/06 ,  H03M1/08

    CPC分类号： H03M1/0872

    摘要： Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.

    摘要翻译： 具有噪声管理的混合信号处理器。 一种具有数字处理部分和模拟部分的混合信号处理器集成电路中的噪声管理方法数字处理部分以第一时钟速率被计时以处理数字数据。 当要由模拟部分执行转换操作时，数字处理部分的时钟在模拟部分的数据转换操作的至少一部分期间被禁止，以防止数字处理部分中的时钟转换的噪声成为 在数据转换操作的至少一部分期间注入模拟部分。

    Method of forming D/A resistor strings with cross coupling switches
    10.
    发明授权
    Method of forming D/A resistor strings with cross coupling switches 有权

    公开(公告)号：US06642877B2

    公开(公告)日：2003-11-04

    申请号：US10217659

    申请日：2002-08-13

    申请人： Ka Y. Leung

    发明人： Ka Y. Leung

    IPC分类号： H03M166

    CPC分类号： H03M1/0663 ,  H03M1/682 ,  H03M1/765

    摘要： A method is disclosed for forming resistor strings in a semiconductor material for a digital-to-analog converter having a main DAC resistor string and a sub-DAC resistor string. The main DAC resistor string is formed as two identical resistor strings connected in parallel and such that the bottom of one resistor string and the top of the other resistor string are connected to a first voltage. The other ends of the resistor strings are coupled to a second different voltage. A switch multiplexer serving two functions is connected between the resistor strings. Each switch of the multiplexer interconnects similar voltage nodes of each resistor string together to thereby average the voltage should the resistance values differ due to semiconductor process variations. The switch multiplexer also serves to select one resistor of each resistor string to couple the voltage thereacross to a sub-resistor string of the digital-to-analog converter.