公开(公告)号：US07659189B2

公开(公告)日：2010-02-09

申请号：US11686961

申请日：2007-03-16

申请人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

发明人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/518 ,  H01L21/28097 ,  H01L21/28229 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/78

摘要： A semiconductor MOS device includes a semiconductor substrate; a gate oxide layer disposed on the semiconductor substrate; a fully silicided gate electrode disposed on the gate oxide layer; a composite thin film interposed between the fully silicided gate electrode and the gate oxide layer; a spacer on sidewall of the fully silicided gate electrode; and a source/drain region implanted into the semiconductor substrate next to the spacer. A method for forming the semiconductor MOS device is disclosed.

摘要翻译： 半导体MOS器件包括半导体衬底; 设置在所述半导体基板上的栅极氧化层; 设置在栅极氧化物层上的完全硅化的栅电极; 插入在完全硅化的栅极电极和栅极氧化物层之间的复合薄膜; 在全硅化物栅电极的侧壁上的间隔物; 以及注入到间隔物旁边的半导体衬底中的源极/漏极区域。 公开了一种用于形成半导体MOS器件的方法。

公开(公告)号：US20090258482A1

公开(公告)日：2009-10-15

申请号：US12101160

申请日：2008-04-11

申请人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

发明人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC分类号： H01L21/283

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

摘要翻译： 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US20090236669A1

公开(公告)日：2009-09-24

申请号：US12052728

申请日：2008-03-20

申请人： Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28079 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.

摘要翻译： 公开了一种用于制造金属栅极晶体管和多晶硅电阻器的方法。 首先，提供具有晶体管区域和电阻器区域的基板。 然后在衬底上形成多晶硅层以覆盖衬底的晶体管区域和电阻器区域。 接下来，去除设置在电阻器中的多晶硅层的一部分，并且对剩余的多晶硅层进行图案化以在布置在晶体管区域中的多晶硅层的表面和设置在电阻器中的多晶硅层的表面之间产生台阶高度 地区。

公开(公告)号：US07589385B2

公开(公告)日：2009-09-15

申请号：US11161170

申请日：2005-07-26

申请人： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

发明人： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

IPC分类号： H01L27/92

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.

摘要翻译： 公开了一种包括拉伸应力NMOS晶体管和PMOS晶体管的CMOS晶体管器件。 NMOS晶体管包括栅极，栅极和半导体衬底之间的栅极氧化物层，栅极侧壁上的氧化硅偏移间隔物，注入到氧化硅偏移间隔物旁边的半导体衬底中的N型轻掺杂源/漏极，N 在N型轻掺杂源极/漏极旁边注入到半导体衬底中的重掺杂源极/漏极，覆盖栅极的拉伸应力氮化硅层，N型轻掺杂源极/漏极和N型重掺杂源极/ 排水。

公开(公告)号：US20090206415A1

公开(公告)日：2009-08-20

申请号：US12033017

申请日：2008-02-19

申请人： Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

发明人： Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

摘要： A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.

摘要翻译： 半导体元件结构包括具有第一高K材料的第一MOS和用于第一栅极的第一金属，具有第二高K材料的第二MOS和用于第二栅极的第二金属和桥接通道 设置在连接第一栅极和第二栅极的凹部中，用于电连接第一栅极和第二栅极，其中桥接通道嵌入在第一栅极和第二栅极中的至少一个栅极中。

公开(公告)号：US20080318371A1

公开(公告)日：2008-12-25

申请号：US12198111

申请日：2008-08-25

申请人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

发明人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843

摘要： A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.

摘要翻译： 半导体器件包括：第一栅极结构，包括直接接触衬底的栅极电介质层，栅极电介质层上的底部电极和底部电极上的顶部电极;以及第二栅极结构，包括直接接触衬底的栅介质层和 栅电介质层上的栅电极。

公开(公告)号：US20080237809A1

公开(公告)日：2008-10-02

申请号：US11693455

申请日：2007-03-29

申请人： Yao-Tsung Huang ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

发明人： Yao-Tsung Huang ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

IPC分类号： H01L29/06 ,  C30B1/00

CPC分类号： H01L29/045 ,  C30B1/023 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7847

摘要： A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.

摘要翻译： 描述了制造混合取向衬底的方法。 提供具有第一取向的硅衬底，其具有直接在其上的第二取向的硅层，然后在硅层上形成应力层。 在硅层的第一部分和第二部分之间通过应力层形成沟槽并进入衬底。 硅层的第一部分是非晶化的。 进行SPE工艺，以将第一取向的硅层的非晶化第一部分重结晶为再结晶层。 在低于1200℃的温度下进行退火处理，以将硅层的第二部分的表面层转变成应变层。 在SPE工艺或退火工艺之后，沟槽中填充有绝缘材料，应力层被去除。

公开(公告)号：US20080220595A1

公开(公告)日：2008-09-11

申请号：US11684634

申请日：2007-03-11

申请人： Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

发明人： Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC分类号： H01L21/04

CPC分类号： H01L21/02694 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02658 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/823807 ,  H01L29/7843

摘要： A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.