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61.发明授权System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel 有权用于将部分高速缓存行读取操作支持到存储器模块以减少存储器通道上的读取数据流量的系统公开(公告)号：US07861014B2
公开(公告)日：2010-12-28
申请号：US11848312
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F11/1048 , G06F12/0879 , G06F12/0888 , G06F13/1684
摘要： A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.
摘要翻译： 提供了一种存储器系统，其支持对存储器模块的部分高速缓存行读取操作以减少存储器通道上的读取数据流量。 存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。 存储器集线器包括集成在存储器集线器设备中的突发逻辑。 突发逻辑确定要从该组存储器件发送的读取数据量，并产生与读取数据量对应的突发长度字段。 存储器集线器还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器控制使用突发长度字段发送的读取数据量。 存储器集线器设备发送等于或小于常规数据突发数据量的读取数据量。
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公开(公告)号：US20100217915A1
公开(公告)日：2010-08-26
申请号：US12390731
申请日：2009-02-23
CPC分类号： G06F11/1004 , G06F12/0886
摘要： A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
摘要翻译： 提供了高可用性的内存系统。 存储器系统包括多个存储器通道。 每个存储器通道包括至少一个存储器模块，其中存储器件被组织为耦合到存储器设备总线段的部分等级。 每个部分等级包括作为存储器设备总线段的子集上的子信道可访问的存储器件的子集。 存储器系统还包括与多个存储器通道通信的存储器控制器。 存储器控制器通过存储器通道分配访问请求以访问完整等级。 完整等级包括在独立内存通道上的至少两个部分等级。 可以同时访问公共内存模块上的部分排名。 存储器模块可以在至少两个可同时访问的部分等级之间使用至少一个校验和存储器设备作为专用校验和存储器设备或共享校验和存储器设备。
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63.发明授权Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem 有权使用嵌入在内存集线器中的缓存来替换内存子系统中的故障内存单元公开(公告)号：US07770077B2
公开(公告)日：2010-08-03
申请号：US12019141
申请日：2008-01-24
IPC分类号： G11C29/00
CPC分类号： G06F12/0802 , G06F11/1666 , G06F11/20 , G11C5/04 , G11C29/808
摘要： A mechanism is provided for using a cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.
摘要翻译： 提供了一种机制，用于使用嵌入在存储器集线器设备中的高速缓存来替换故障存储器单元。 存储器模块包括集成存储器集线器设备。 存储器集线器设备包括与耦合到存储器集线器设备的一组存储器设备和集成在存储器集线器设备中的高速缓存器通信的集成存储器设备数据接口。 存储器集线器设备还包括集成存储器集线器控制器，其基于确定存储器装置集合内的一个或多个存储器单元是否已经失败来控制由存储器件数据接口读取或写入高速缓存的数据。
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64.发明授权System, method and storage medium for providing a serialized memory interface with a bus repeater 失效用于向总线中继器提供串行存储器接口的系统，方法和存储介质公开(公告)号：US07765368B2
公开(公告)日：2010-07-27
申请号：US11773660
申请日：2007-07-05
CPC分类号： G06F13/4022
摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.
摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。
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65.发明申请System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel 有权用于存储通道的组合纠错码和循环冗余校验码的系统公开(公告)号：US20090193315A1
公开(公告)日：2009-07-30
申请号：US12018926
申请日：2008-01-24
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
CPC分类号： H03M13/09 , G06F11/1004
摘要： A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.
摘要翻译： 提供了一种在存储器级别进行纠错的存储器系统。 存储器系统包括集成在存储器模块中的存储器集线器设备和集成在存储器集线器设备中的链路接口，其提供存储器集线器设备和外部存储器控制器之间的通信路径。 链路接口包括集成在链路接口中的第一纠错逻辑，其对经由要发送到一组存储器装置的第一存储器信道从外部存储器控制器接收到的第一数据执行纠错操作。 第一纠错逻辑响应于第一纠错逻辑检测第一数据中的第一误差，向外部存储器控制器产生第一误差信号。 链路接口控制逻辑集成在链路接口中，控制将第一个数据传输到一组存储器件。
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66.发明申请Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel 失效支持部分高速缓存行读写操作到存储器模块的方法，以减少内存通道上的读写数据流量公开(公告)号：US20090063731A1
公开(公告)日：2009-03-05
申请号：US11850290
申请日：2007-09-05
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/28
摘要： A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices.
摘要翻译： 提供了一种方法，其支持对存储器模块的部分高速缓存行读和写操作，以减少存储器通道上的读和写数据流量。 集成在存储器模块中的存储器集线器控制器响应于访问请求确定要发送到存储器模块的一组存储器设备的数据量。 存储器集线器控制器产生对应于数据量的突发长度字段。 存储器控制器使用突发长度字段控制发送到存储器件或从存储器件传输的数据量。 数据量等于或小于该组存储器件的标准数据突发数据量。
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67.发明申请System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel 失效支持部分高速缓存线写入操作到内存模块的系统，以减少内存通道上的写入数据流量公开(公告)号：US20090063730A1
公开(公告)日：2009-03-05
申请号：US11848342
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
CPC分类号： G06F13/161
摘要： A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.
摘要翻译： 提供了一种存储器系统，其支持对存储器模块的部分高速缓存行写入操作以减少存储器通道上的写入数据流量。 存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。 存储器集线器设备包括集成在存储器集线器设备中的突发逻辑。 突发逻辑确定要发送到存储器装置集合的写入数据量，并产生与写入数据量对应的突发长度字段。 存储器集线器还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器控制使用突发长度字段发送的写入数据量。 存储器集线器设备发送等于或小于常规数据突发量的写入数据量。
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68.发明授权System, method and storage medium for providing fault detection and correction in a memory subsystem 有权用于在存储器子系统中提供故障检测和校正的系统，方法和存储介质公开(公告)号：US07484161B2
公开(公告)日：2009-01-27
申请号：US11851485
申请日：2007-09-07
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
IPC分类号： H03M13/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.
摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。
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69.发明授权System, method and storage medium for providing fault detection and correction in a memory subsystem 失效用于在存储器子系统中提供故障检测和校正的系统，方法和存储介质公开(公告)号：US07331010B2
公开(公告)日：2008-02-12
申请号：US10977914
申请日：2004-10-29
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
IPC分类号： G11C29/52
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.
摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。
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70.发明授权Providing frame start indication in a memory system having indeterminate read data latency 有权在具有不确定的读数据延迟的存储器系统中提供帧起始指示公开(公告)号：US08495328B2
公开(公告)日：2013-07-23
申请号：US13397827
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero.
摘要翻译： 一种用于提供帧开始指示的方法，包括经由存储器系统中的信道接收数据传送。 接收是响应于请求，并且在相对于请求的不确定的时间。 确定数据传输是否包括帧起始指示符。 响应于确定数据传输包括帧起始指示符，捕获数据传输和“n”个后续数据传输。 数据传输和“n”个后续数据传输构成数据帧，其中“n”大于零。
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