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61.发明授权System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture 失效系统和方法能够使稳定的存储优势与稳定的存储架构相结合公开(公告)号：US06963967B1
公开(公告)日：2005-11-08
申请号：US09588508
申请日：2000-06-06
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.
摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。
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62.发明授权High performance symmetric multiprocessing systems via super-coherent data mechanisms 失效通过超相干数据机制的高性能对称多处理系统公开(公告)号：US06785774B2
公开(公告)日：2004-08-31
申请号：US09978362
申请日：2001-10-16
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.
摘要翻译： 一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得 请求处理器使用超相干数据执行操作。 数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。 数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。 当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。 如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用 本地缓存内的数据，不发给系统互连。 通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。 每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。
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63.发明授权System and method for asynchronously overlapping storage barrier operations with old and new storage operations 有权使用旧的和新的存储操作异步重叠存储屏障操作的系统和方法公开(公告)号：US06609192B1
公开(公告)日：2003-08-19
申请号：US09588607
申请日：2000-06-06
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.
摘要翻译： 公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。 数据处理系统包括存储器和耦合到互连的多个处理器。 至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。 指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。 还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。 然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。 或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。 负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前 操作。
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64.发明授权Symmetric multiprocessor systems with an independent super-coherent cache directory 失效具有独立超级相干缓存目录的对称多处理器系统公开(公告)号：US06779086B2
公开(公告)日：2004-08-17
申请号：US09978363
申请日：2001-10-16
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which contains a subset of cache line addresses from the main cache directory corresponding to cache lines that are in a first or second coherency state, where the second coherency state indicates to the first processor that requests issued from the first processor for a cache line whose address is within the secondary directory should utilize super-coherent data currently available in the first cache and should not be issued on the system interconnect. Additionally, the cache controller logic includes a clear on barrier flag (COBF) associated with the secondary directory, which is set whenever an operation of the first processor is issued to said system interconnect. If a barrier instruction is received by the first processor while the COBF is set, the contents of the secondary directory are immediately flushed and the cache lines are tagged with an invalid state.
摘要翻译： 一种多处理器数据处理系统，除了具有相应的第一和第二高速缓存以及隶属于第一处理器的高速缓存的主缓存目录的第一处理器和第二处理器之外，还包括第一高速缓存的副高速缓存目录，其包含高速缓存行的子集 来自对应于处于第一或第二相关性状态的高速缓存行的主缓存目录的地址，其中第二一致性状态向第一处理器指示从第一处理器发出的对于地址在次目录内应该利用的高速缓存行的请求 超级相干数据目前在第一个缓存中可用，不应在系统互连上发布。 此外，高速缓存控制器逻辑包括与副目录相关联的清除屏障标志（COBF），其随着第一处理器的操作被发布到所述系统互连而被设置。 如果在设置COBF时由第一处理器接收到屏障指令，则立即刷新副目录的内容，并将高速缓存行标记为无效状态。
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公开(公告)号：US06763435B2
公开(公告)日：2004-07-13
申请号：US09978355
申请日：2001-10-16
IPC分类号： G06F1314
CPC分类号： G06F12/0831
摘要： A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.
摘要翻译： 一种用于提高多处理器数据处理系统的性能的方法，包括：窥探在所述数据处理系统的系统总线上的共享高速缓存行中保存的数据的请求，所述数据处理系统的高速缓存包含所述共享高速缓存行的更新副本，并响应于所述 第二处理器的请求，在系统总线上发出第一响应，向请求处理器指示请求处理器可以利用当前存储在请求处理器的高速缓存的共享高速缓存行中的数据。 当请求被第二处理器窥探并且第二处理器决定释放到请求处理器的高速缓存行上的锁时，第二处理器在系统总线上发出指示第一处理器应该利用新的/相干数据的第二响应， 那么第二处理器将锁定释放到第一处理器。
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66.发明授权Data processing system and method for resolving a conflict between requests to modify a shared cache line 失效用于解决修改共享缓存行的请求之间的冲突的数据处理系统和方法公开(公告)号：US06763434B2
公开(公告)日：2004-07-13
申请号：US09752947
申请日：2000-12-30
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data is complete. The data processing system includes a plurality of agents coupled to an interconnect that supports pipelined transactions. While data associated with a target address are cached at a first agent among the plurality of agents in a shared state, the first agent issues a transaction on the interconnect. In response to snooping the transaction, a second agent provides a snoop response indicating that the second agent has a pending conflicting request and a coherency decision point provides a snoop response granting the first agent ownership of the data. In response to the snoop responses, the first agent is provided with a combined response representing a collective response to the transaction of all of the agents that grants the first agent ownership of the data. In response to the combined response, the first agent is permitted to modify the data.
摘要翻译： 这里公开了一种数据处理系统和方法，该数据处理系统和方法在数据处理系统之间进行仲裁，以便在冲突的请求之间进行仲裁，以修改在共享状态下缓存的数据，并保护在此类仲裁期间授予的高速缓存行的所有权，直到数据修改完成。 数据处理系统包括耦合到支持流水线交易的互连的多个代理。 虽然与目标地址相关联的数据在共享状态的多个代理之间的第一代理处被高速缓存，但第一代理在互连上发布事务。 响应于窥探事务，第二代理提供窥探响应，指示第二代理具有待决冲突请求，并且一致性决策点提供准备数据的第一代理所有权的窥探响应。 响应于窥探响应，向第一代理提供组合的响应，其表示对授予数据的第一代理所有权的所有代理的交易的集体响应。 响应于组合的响应，允许第一代理修改数据。
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公开(公告)号：US06691220B1
公开(公告)日：2004-02-10
申请号：US09588608
申请日：2000-06-06
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3859
摘要： A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.
摘要翻译： 一种处理器内的操作方法，其允许按照指令序列中的障碍指令之后的加载指令进行推测。 屏障指令被执行，并且当屏障操作正在等待时，推测地发出与加载指令相关联的加载请求。 设置了一个猜测标志来指示加载指令被推测发出。 当接收到屏障操作的确认时，该标志被复位。 在接收到确认之前返回的数据被暂时保留，并且仅在接收到确认之后将数据转发到处理器的寄存器和/或执行单元。 如果在屏障操作完成之前，对于推测发出的负载请求检测到窥探无效，则丢弃数据并重新发出加载请求。
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68.发明授权公开(公告)号：US06658539B2
公开(公告)日：2003-12-02
申请号：US09978353
申请日：2001-10-16
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/084
摘要： A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state. This state indicates that subsequent requests for the cache line by the first processor should be provided said super-coherent data, while a subsequent request for the cache line by a next processor in the processor group that has not yet issued a request for the cache line on the system bus, may still go to the system bus to request the cache line. The individualized, processor-specific super coherency states are individually set but are usually changed to another coherency state (e.g., Modified or Invalid) as a group.
摘要翻译： 一种用于改善具有处理器组与共享高速缓存的多处理器数据处理系统的性能的方法。 当共享缓存的处理器组内的处理器窥探在处理器组内的另一处理器的高速缓存中的共享高速缓存线的修改时，第一高速缓存内的共享高速缓存行的一致性状态被设置为第一 指示高速缓存行已被处理器组内的处理器修改并且高速缓存行尚未在组的高速缓存内更新的一致性状态。 当稍后由处理器发出对高速缓存行的请求时，该请求被发布到系统总线或互连。 如果对该请求的接收到的响应指示处理器应该使用超相干数据，则高速缓存行的一致性状态被设置为处理器特定的超一致性状态。 该状态指示应该为所述超相干数据提供由第一处理器对高速缓存行的后续请求，而处理器组中尚未发出对高速缓存行请求的下一个处理器对高速缓存行的后续请求 在系统总线上，仍然可以去系统总线请求缓存行。 个性化的处理器特定的超一致性状态是单独设置的，但是通常作为一组更改为另一个一致性状态（例如，修改或无效）。
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69.发明授权Multiprocessor speculation mechanism for efficiently managing multiple barrier operations 有权用于有效管理多个屏障操作的多处理器推测机制公开(公告)号：US06625660B1
公开(公告)日：2003-09-23
申请号：US09588605
申请日：2000-06-06
IPC分类号： G06F1516
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3867
摘要： Disclosed is a method of operation within a processor that permits load instructions to be issued speculatively. An instruction sequence is received that includes multiple barrier instructions and a load instruction that follows the barrier instructions in the instruction sequence. In response to the multiple barrier instructions, barrier operations are issued on an interconnect coupled to the processor. Also, while the barrier operations are pending, a load request associated with the load instruction is speculatively issued. When the load request is issued, a flag is set to indicate that it was speculatively issued. The flag is reset when acknowledgments of all the barrier operations are received. Data that is returned before the acknowledgments are received is temporarily held and forwarded to the register and/or execution unit of the processor only after the acknowledgments are received. If a snoop invalidate is detected for the speculatively issued load request before completion of the barrier operations, the data is discarded and the load request is re-issued.
摘要翻译： 公开了一种在处理器内操作的方法，其允许以推测方式发布加载指令。 接收包括多个屏障指令和跟随指令序列中的屏障指令的加载指令的指令序列。 响应于多个屏障指令，在耦合到处理器的互连上发出屏障操作。 此外，当屏障操作正在等待时，推测性地发出与加载指令相关联的加载请求。 当发出加载请求时，会设置一个标志来指示它被推测发出。 当接收到所有屏障操作的确认时，该标志被复位。 在接收到确认之前返回的数据被暂时保存，并且在接收到确认之后被转发到处理器的寄存器和/或执行单元。 如果在完成屏障操作之前，对于推测发出的加载请求检测到窥探无效，则丢弃数据并重新发出加载请求。
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70.发明授权System bus structure for large L2 cache array topology with different latency domains 失效具有不同延迟域的大二级缓存阵列拓扑的系统总线结构公开(公告)号：US08015358B2
公开(公告)日：2011-09-06
申请号：US12207393
申请日：2008-09-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译： 一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分 总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。 在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组 线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。
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