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    Memory Circuitry And Method Used In Forming Memory Circuitry
    61.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240071496A1

    公开(公告)日：2024-02-29

    申请号：US17897460

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

    Integrated assemblies and methods of forming integrated assemblies
    63.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US11910596B2

    公开(公告)日：2024-02-20

    申请号：US17223254

    申请日：2021-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

    BARRIER STRUCTURE FOR PREVENTING ETCHING TO CONTROL CIRCUITRY
    64.
    发明公开
    BARRIER STRUCTURE FOR PREVENTING ETCHING TO CONTROL CIRCUITRY 审中-公开

    公开(公告)号：US20230380172A1

    公开(公告)日：2023-11-23

    申请号：US17748924

    申请日：2022-05-19

    Applicant: Micron Technology, Inc.

    Inventor： John Hopkins ,  Jordan D. Greenlee ,  Daniel Billingsley ,  Alyssa N. Scarbrough

    IPC: H01L27/11573 ,  H01L27/11529

    CPC classification number: H01L27/11573 ,  H01L27/11529

    Abstract: Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.

    Memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells
    67.
    发明授权
    Memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11641737B2

    公开(公告)日：2023-05-02

    申请号：US17162062

    申请日：2021-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/48 ,  H01L23/522 ,  G11C5/06

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Simultaneously, (a), (b), and (c) are formed, where (a): horizontally-elongated trenches into the stack laterally-between immediately-laterally-adjacent of the memory-block regions; (b): channel openings into the stack laterally-between the horizontally-elongated trenches; and (c): through-array-via (TAV) openings into the stack in a stair-step region. Intervening material is formed in the horizontally-elongated trenches, a channel-material string in individual of the channel openings, and conductive material in the TAV openings. Other aspects, including structure independent of method, are disclosed.

    Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    70.
    发明申请
    Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210358929A1

    公开(公告)日：2021-11-18

    申请号：US15931116

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

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